Intel 80C186EA User Manual Page 37
- Page / 50
- Table of contents
- BOOKMARKS
- October 1995 1
- COPYRIGHT 1
- INTEL CORPORATION, 1995 1
- Order Number: 272432-003 1
- 272432–1 1
- CONTENTS PAGE 2
- 272432–2 3
- INTRODUCTION 4
- 80C186EA CORE ARCHITECTURE 4
- Bus Interface Unit 4
- Clock Generator 4
- 80C186EA PERIPHERAL 5
- ARCHITECTURE 5
- Interrupt Control Unit 5
- Timer/Counter Unit 5
- 00H Reserved 6
- 40H Reserved 6
- 80H Reserved 6
- C0H DMA0 Src. Lo 6
- DMA Control Unit 7
- Chip-Select Unit 7
- Refresh Control Unit 7
- Power Management 7
- PACKAGE INFORMATION 9
- Pin Descriptions 9
- 80C186EA PINOUT 15
- NOTES: 272432–5 16
- NOTES: 272432–6 18
- PACKAGE THERMAL 20
- SPECIFICATIONS 20
- ELECTRICAL SPECIFICATIONS 21
- Absolute Maximum Ratings* 21
- Recommended Connections 21
- AC SPECIFICATIONS 25
- AC SPECIFICATIONS (Continued) 26
- AC TEST CONDITIONS 30
- AC TIMING WAVEFORMS 30
- 272432–12 32
- DERATING CURVES 33
- 272432–15 34
- 272432–16 35
- BUS CYCLE WAVEFORMS 36
- 272432-18 37
- 272432–19 38
- NOTES: 272432–20 39
- Figure 21. HOLD/HLDA Waveform 40
- 272432–22 41
- Figure 23. Ready Waveform 42
- 80C186EA/80C188EA EXECUTION 43
- INSTRUCTION SET SUMMARY 44
- (Continued) 45
- REVISION HISTORY 50
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