Intel 386 User Manual download pdf (Page 76)

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5-3

DEVICE CONFIGURATION

5.2 PERIPHERAL CONFIGURATION

This section describes the configuration of each on-chip peripheral. For more detailed informa-

tion on the peripheral itself, see the chapter describing that peripheral.

The symbology used for signals that share a device pin is shown in Figure 5-2. Of the two signal

names by a pin, the upper signal is associated with the peripheral in the figure. The lower signal

in parentheses is the alternate signal, which connects to a different peripheral or the core. When

a pin has a multiplexer, it is shown as a switch, and the register bit that controls it is noted above

the switch.

5.2.1 DMA Controller, Bus Arbiter, and Refresh Unit Configuration

Figure 5-2 shows the DMA controller, bus arbiter, and refresh unit configuration. Requests for a

DMA data transfer are shown as inputs to the multiplexer:

• A serial I/O transmitter (TXEDMA0, TXEDMA1) or receiver (RBFDMA0, RBFDMA1)

• A synchronous serial I/O transmitter (SSTBE) or receiver (SSRBF)

• A timer (OUT1, OUT2)

• An external source (DRQ0, DRQ1)

The inputs are selected by the DMA configuration register (see Figure 5-3).

5.2.1.1 Using The DMA Unit with External Devices

For each DMA channel, three bits in the DMA configuration register (Figure 5-3) select the ex-

ternal request input or one of seven request inputs from the peripherals. Another bit enables or

disables that channel’s DMA acknowledge signal (DACKn#) at the device pin. Enable the

DACKn# signal only when you are using the external request signal (DRQn) and need DACKn#.

The acknowledge signals are not routed to the on-chip peripherals, and therefore, these peripher-

als cannot initiate single-cycle (fly-by) DMA transfers.

An external bus master cannot talk directly to internal peripheral modules because the external

address lines are outputs only. However, an external device could use a DMA channel to transfer

data to or from an internal peripheral because the DMA generates the addresses. This transaction

would be a two-cycle DMA bus transaction.

5.2.1.2 DMA Service to an SIO or SSIO Peripheral

A DMA unit is useful for servicing an SIO or SSIO peripheral operating at a high baud rate. At

high baud rates, the interrupt response time of the core may be too long to allow the serial

channels to use an interrupt to service the receive-buffer-full condition. By the time the interrupt

service routine (ISR) is ready to transfer the receive-buffer data to memory, new data would have

been loaded into the buffer. The issue is the interrupt latency which is the amount of time the

processor takes from recognizing the interrupt to executing the first line of code in the ISR. This

interrupt latency needs to be calculated to determine if an ISR can handle the high baud rate. If

the Interrupt Latency is too high, data transfers to and from the serial channels can occur within

a few bus cycles of the time that a serial unit is ready to move data by using an appropriately

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