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8-5
CLOCK AND POWER MANAGEMENT UNIT
Figure 8-3. SMM Interaction with Idle and Powerdown Modes
8.1.2.2 Bus Interface Unit Operation During Idle Mode
The bus interface unit (BIU) can process DMA, DRAM refresh, and external hold requests during
idle mode. When the first request occurs, the core wakes up long enough to relinquish bus control
to the bus arbiter, then returns to idle mode. For the remaining time in idle mode, the bus arbiter
controls the bus. DMA, DRAM refresh, and external hold requests are processed in the same way
as during normal operation.
8.1.2.3 Watchdog Timer Unit Operation During Idle Mode
When the watchdog timer unit is in system watchdog mode, idle mode stops the down-counter.
Since no software can run while the CPU is idle, a software watchdog is not needed. When it is
in bus monitor or general-purpose timer mode, the watchdog timer unit continues to run while the
device is in idle mode. (Chapter 17 describes the watchdog timer unit.)
Reset or
RSM Instruction
with Halt Restart
Slot Clear
System
Management
Mode
Powerdown
Mode
Idle
Mode
Normal
Operation
SMI#
A2229-03
Halt Instruction
with Idle Flag Set
RSM Instruction
with Idle Flag and
Halt Restart Slot Set
SMI#
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Halt Instruction
with Powerdown
Flag Set
RSM with
Powerdown Flag
and Halt Restart
Slot Set
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SMI#
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- Intel386 1
- Embedded Microprocessor 1
- User’s Manual 1
- Intel386 EX 2
- Embedded 2
- Microprocessor 2
- User’s Manual 2
- GUIDE TO THIS 26
- CHAPTER 1 28
- GUIDE TO THIS MANUAL 28
- Packaging 32
- ARCHITECTURAL 36
- OVERVIEW 36
- CHAPTER 2 38
- ARCHITECTURAL OVERVIEW 38
- A2849-02 39
- 2.2 INTEGRATED PERIPHERALS 40
- IEEE Standard Test 41
- CORE OVERVIEW 42
- CHAPTER 3 44
- A2850-01 45
- REGISTER 50
- ORGANIZATION 50
- CHAPTER 4 52
- SYSTEM REGISTER ORGANIZATION 52
- A2499-02 55
- A2495-02 61
- A2496-02 63
- A2502-02 65
- CONFIGURATION 72
- CHAPTER 5 74
- A2535-01 75
- • A timer (OUT1, OUT2) 76
- A2517-03 85
- A2518-02 91
- A3380-01 93
- 5.2.7 Core Configuration 94
- DEVICE CONFIGURATION 100
- • Interrupt Control Unit: 101
- • Timer Control Unit: 101
- BUS INTERFACE 112
- CHAPTER 6 114
- BUS INTERFACE UNIT 114
- 6.1.1 Bus Signal Descriptions 116
- A2305-02 119
- A2484-02 121
- Figure 6-3. Ready Logic 124
- A2486-03 125
- A2488-02 131
- READY# Asserted • 133
- HOLD Asserted 133
- • NA# is ignored 136
- Figure 6-10. Halt Cycle 140
- A2493-02 143
- 6.3.7.1 Write Cycles 144
- 6.3.7.2 Read Cycles 144
- A3375-01 146
- 6.6.1.1 System Configuration 152
- A2854-02 155
- A3265-02 157
- MANAGEMENT 158
- CHAPTER 7 160
- SYSTEM MANAGEMENT MODE 160
- A2510-02 164
- A2512-02 165
- 7.3.2.1 SMI# Priority 166
- A2508-01 167
- A2509-01 168
- A2511-02 169
- A2505-02 170
- A2507-01 171
- 7.3.4.2 SMRAM State Dump Area 173
- CLOCK AND 180
- CHAPTER 8 182
- A2470-02 183
- A2229-03 186
- 8.4.2.1 Built-in Self Test 193
- 8.4.2.2 JTAG Reset 193
- INTERRUPT 198
- CONTROL UNIT 198
- CHAPTER 9 200
- INTERRUPT CONTROL UNIT 200
- 9.2.2.2 Determining Priority 206
- A2428-01 211
- • A poll command is issued 213
- A2430-01 228
- Data Bus 228
- Vector Number 228
- IR (Valid) 229
- IR sampled on this edge 229
- IR (Spurious) 229
- A2857-01 230
- // Vector Table 238
- TIMER/COUNTER 242
- CHAPTER 10 244
- TIMER/COUNTER UNIT 244
- A2317-02 245
- Table 10-1. TCU Signals 246
- A2395-02 251
- A2312-02 252
- • A gate trigger 253
- • The counter reaches one 253
- A2400-01 257
- ????864286410 258
- A2315-01 259
- A2316-01 261
- Table 10-4. GATE 263
- Connection Options 263
- 10.3.4.1 Simple Read 270
- Figure 10-28. Timer 272
- Register (TMR 272
- – Read Format) 272
- Figure 10-30. Timer 275
- – Status Format) 275
- • With the readback command: 277
- ASYNCHRONOUS 286
- SERIAL I/O UNIT 286
- CHAPTER 11 288
- ASYNCHRONOUS SERIAL I/O UNIT 288
- A2519-02 289
- 11.1.1 SIO Signals 290
- Figure 11-2. SIO 291
- Table 11-1. SIO Signals 291
- Figure 11-3. SIO 294
- Transmitter 294
- Figure 11-4. SIO 295
- Figure 11-5. SIO 296
- Receiver 296
- A2525-02 298
- 11.2.6.2 SIO DMA sources 300
- 11.3 REGISTER DEFINITIONS 302
- = 1–3]) 304
- and DLH 309
- CONTROLLER 334
- CHAPTER 12 336
- DMA CONTROLLER 336
- A2531-02 337
- 12.1.2 DMA Signals 339
- 12.2.2.1 Fly-By Mode 340
- 12.2.2.2 Two-Cycle Mode 341
- A3381-01 343
- A2480-02 344
- A2332-02 351
- A2333-02 355
- A2338-02 357
- A2336-02 359
- Figure 12-17. Cascade Mode 361
- 12.3 REGISTER DEFINITIONS 363
- (read format) 378
- (Address) 385
- Command Functions 385
- DWORD lAddress; 390
- SYNCHRONOUS 398
- CHAPTER 13 400
- SYNCHRONOUS SERIAL I/O UNIT 400
- A2435-02 401
- A2436-02 402
- 13.1.1 SSIO Signals 403
- Baud-rate Value 405
- A3398-01 409
- (Enabled when Clock is High) 410
- (Enabled when Clock is Low) 410
- 13.2.2.2 Autotransmit Mode 411
- 13.2.2.3 Slave Mode 411
- A3397-01 413
- 13.3 REGISTER DEFINITIONS 415
- (BCLKIN) 417
- SSIO Example Code 425
- CHIP-SELECT 434
- CHAPTER 14 436
- CHIP-SELECT UNIT 436
- A2534-01 439
- A2392-02 447
- ADH, UCSADH) 452
- ADL, UCSADL) 453
- MSKH, UCSMSKH) 454
- MSKL, UCSMSKL) 455
- REFRESH 460
- CHAPTER 15 462
- REFRESH CONTROL UNIT 462
- 15.4 REGISTER DEFINITIONS 467
- INPUT/OUTPUT 478
- CHAPTER 16 480
- INPUT/OUTPUT PORTS 480
- 16.1.1 Port Functionality 481
- Table 16-1. Pin Multiplexing 484
- 16.2 REGISTER DEFINITIONS 485
- 16.4.1 I/O Ports Code Example 490
- WATCHDOG 494
- TIMER UNIT 494
- CHAPTER 17 496
- WATCHDOG TIMER UNIT 496
- A2330-02 497
- Table 17-1. WDT Signals 498
- 17.4 REGISTER DEFINITIONS 502
- JTAG TEST-LOGIC 512
- CHAPTER 18 514
- JTAG TEST-LOGIC UNIT 514
- A2340-01 515
- A2356-01 519
- × 2 cells) 522
- 18.4 TIMING INFORMATION 525
- DESCRIPTIONS 528
- APPENDIX A 530
- SIGNAL DESCRIPTIONS 530
- COMPATIBILITY 540
- WITH THE PC/AT* 540
- ARCHITECTURE 540
- APPENDIX B 542
- COMPATIBILITY WITH THE PC/AT* 542
- MASTER# 544
- (From PC/AT* Bus) 544
- Processor 544
- EXAMPLE CODE 548
- HEADER FILES 548
- APPENDIX C 550
- EXAMPLE CODE HEADER FILES 550
- C.2 EXAMPLE CODE DEFINES 555
- REGISTER QUICK 564
- REFERENCE 564
- APPENDIX D 566
- D.2 CLKPRS 572
- ADH (UCSADH) 573
- ADL (UCSADL) 574
- MSKH (UCSMSKH) 575
- MSKL (UCSMSKL) 576
- AND DLH 577
- D.8 DMABSR 578
- D.9 DMACFG 579
- D.10 DMACHR 580
- D.11 DMACMD1 581
- D.12 DMACMD2 582
- D.13 DMAGRPMSK 583
- D.14 DMAIEN 584
- D.15 DMAIS 585
- D.16 DMAMOD1 586
- D.17 DMAMOD2 587
- D.18 DMAMSK 588
- D.20 DMAOVFE 590
- D.21 DMASRR 591
- (write format) 591
- D.22 DMASTS 592
- D.23 ICW1 (MASTER AND SLAVE) 593
- D.24 ICW2 (MASTER AND SLAVE) 594
- D.25 ICW3 (MASTER) 594
- D.26 ICW3 (SLAVE) 595
- D.27 ICW4 (MASTER AND SLAVE) 595
- D.28 IDCODE 596
- D.29 IER 597
- D.30 IIR 598
- D.31 INTCFG 599
- D.33 LCR 601
- D.34 LSR 602
- D.35 MCR 603
- D.36 MSR 604
- D.37 OCW1 (MASTER AND SLAVE) 605
- D.38 OCW2 (MASTER AND SLAVE) 606
- D.39 OCW3 (MASTER AND SLAVE) 607
- D.40 P1CFG 608
- D.41 P2CFG 609
- D.42 P3CFG 610
- D.43 PINCFG 611
- D.47 POLL (MASTER AND SLAVE) 614
- D.48 PORT92 615
- D.49 PWRCON 616
- D.50 RBR 617
- D.51 REMAPCFG 618
- D.52 RFSADD 619
- D.53 RFSBAD 619
- D.54 RFSCIR 620
- D.55 RFSCON 620
- D.56 SCR 621
- D.57 SIOCFG 622
- D.58 SSIOBAUD 623
- D.59 SSIOCON1 624
- D.60 SSIOCON2 625
- D.61 SSIOCTR 626
- D.62 SSIORBUF 626
- D.63 SSIOTBUF 627
- D.64 TBR 627
- D.65 TMRCFG 628
- D.66 TMRCON 629
- D.67 TMR 630
- D.72 WDTCNTH AND WDTCNTL 633
- D.73 WDTRLDH AND WDTRLDL 634
- D.74 WDTSTATUS 635
- INSTRUCTION SET 636
- APPENDIX E 638
- INSTRUCTION SET SUMMARY 638
- Wait states: 639
- Instruction Format 640
- Clock Count Notes 640
- ≤ IOPL. If CPL 658
- GLOSSARY 670
- Glossary-2 673
- Glossary-4 675
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