Intel SSDSC2BB240G4 Datasheet download pdf (Page 17)

Intel® Solid-State Drive DC S3500

April 2013 Product Specification

Order Number: 328860-001US 17

Table 17. Serial ATA Power Pin Definitions—1.8-inch Form Factors

Function

Definition

Mating Order

3.3 V Power

Mate

3.3 V Power, per-charge

Mate

Ground

Mate

Ground

Mate

5 V Power; not connected.

Mate

5 V Power; not connected.

Mate

DAS/DSS

Device Activity Signal/Disable Staggered Spin-up

Mate

Key

Optional

Manufacturing Test Pin

Mate

Optional

Manufacturing Test Pin

Mate

Notes:

1. All mate sequences assume zero angular offset between connectors.

2. P1 and P2 are internally connected to one another within the device.

3. Ground connectors P3 and P4 may contact before the other 1st mate pins in both the power and signal connectors to dis-

charge ESD in a suitably configure backplane connector.

4. Pins P5 and P6 are not connected internally to the device but there is an option to connect through a zero ohm stuffing

resistor. The host may put 5V on these pins.

5. The host may ground P7 if it is not used for Device Activity Signal (DAS).

6. P8 and P9 should not be connected by the host.

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Intel SSDSC2BB240G4 Datasheet Page 17