Intel Core 2 Quad Q6700 Datasheet download pdf (Page 64)

Land Listing and Signal Descriptions

64 Datasheet

D[63:0]#

Input/

Output

D[63:0]# (Data) are the data signals. These signals provide a 64-

bit data path between the processor FSB agents, and must connect

the appropriate pins/lands on all such agents. The data driver

asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will, thus, be driven four

times in a common clock period. D[63:0]# are latched off the falling

edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16

data signals correspond to a pair of one DSTBP# and one DSTBN#.

The following table shows the grouping of data signals to data

strobes and DBI#.

Furthermore, the DBI# signals determine the polarity of the data

signals. Each group of 16 data signals corresponds to one DBI#

signal. When the DBI# signal is active, the corresponding data

group is inverted and therefore sampled active high.

DBI[3:0]#

Input/

Output

DBI[3:0]# (Data Bus Inversion) are source synchronous and

indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals

are activated when the data on the data bus is inverted. If more

than half the data bits, within a 16-bit group, would have been

asserted electrically low, the bus agent may invert the data bus

signals for that particular sub-phase for that 16-bit group.

DBR# Output

DBR# (Debug Reset) is used only in processor systems where no

debug port is implemented on the system board. DBR# is used by a

debug port interposer so that an in-target probe can drive system

reset. If a debug port is implemented in the system, DBR# is a no

connect in the system. DBR# is not a processor signal.

DBSY#

Input/

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for

driving data on the processor FSB to indicate that the data bus is in

use. The data bus is released after DBSY# is de-asserted. This

signal must connect the appropriate pins/lands on all processor FSB

agents.

Table 25. Signal Description (Sheet 3 of 9)

Name Type Description

Quad-Pumped Signal Groups

Data Group

DSTBN#/

DSTBP#

DBI#

D[15:0]# 0 0

D[31:16]# 1 1

D[47:32]# 2 2

D[63:48]# 3 3

DBI[3:0] Assignment To Data Bus

Bus Signal Data Bus Signals

DBI3# D[63:48]#

DBI2# D[47:32]#

DBI1# D[31:16]#

DBI0# D[15:0]#

1 2 ... 59 60 61 62 63 64 65 66 67 68 69 ... 97 98

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Intel Core 2 Quad Q6700 Datasheet Page 64

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