Intel RH80532NC033256 Datasheet download pdf (Page 55)

Mobile Intel

®

Celeron

®

Processor (0.13 µ)

Micro-FCBGA and Micro-FCPGA Packages Datasheet

298517-006 Datasheet 55

Figure 18.Test Timings (Boundary Scan)

TCK

TDI, TMS

Input

Signals

TDO

Output

Signals

0.75V

T

v

T

w

T

r

T

s

T

x

T

u

T

y

T

z

D0008-01

NOTES:

T

r

=T43 (All Non-Test Inputs Setup Time)

T

s

=T44 (All Non-Test Inputs Hold Time)

T

u

=T40 (TDO Float Delay)

T

v

=T37 (TDI, TMS Setup Time)

T

w

= T38 (TDI, TMS Hold Time)

T

x

=T39 (TDO Valid Delay)

T

y

=T41 (All Non-Test Outputs Valid Delay)

T

z

=T42 (All Non-Test Outputs Float Delay)

Figure 19. Test Reset Timings

TRST#

0.75V

T

q

D0009-01

NOTE:

T

q

=T36 (TRST# Pulse Width)

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 97 98

Comments to this Manuals

No comments