Intel RH80532NC033256 Datasheet Page 50

  • Download
  • Add to my manuals
  • Print
  • Page
    / 98
  • Table of contents
  • BOOKMARKS
  • Rated. / 5. Based on customer reviews
Page view 49
Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
50 Datasheet 298517-006
Figure 11. BCLK/BCLK# Waveform (Differential Mode)
0V
T6
T5
T1
V4
V5
V
IH_DIFF
V
Il_DIFF
Figure 12. Valid Delay Timings
CLK
Signal
T
X
T
x
T
PW
V Valid Valid
D0004-00
Vc Vc
NOTES:
T
x
= T7, T11, T29 (Valid Delay)
T
pw
= T14, T14B (Pulse Width)
V = V
REF
for AGTL signal group; 1.0V for CMOS, Open-drain, APIC, and TAP signal groups
Vc = Crossing point of BCLK rising edge and BCLK# falling edge for BCLK references (Differential Clock)
= 1.25V (Single Ended Clock)
Page view 49
1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 97 98

Comments to this Manuals

No comments