Intel LE80537VE001512 Datasheet download pdf (Page 24)

Errata

24 Specification Update

AR17. Writing Shared Unaligned Data that Crosses a Cache Line without

Proper Semaphores or Barriers May Expose a Memory Ordering Issue

Problem: Software which is written so that multiple agents can modify the same shared

unaligned memory location at the same time may experience a memory ordering

issue if multiple loads access this shared data shortly thereafter. Exposure to this

problem requires the use of a data write which spans a cache line boundary.

Implication: This erratum may cause loads to be observed out of order. Intel has not observed this

erratum with any commercially available software or system.

Workaround: Software should ensure at least one of the following is true when modifying shared

data by multiple agents:

• The shared data is aligned.

• Proper semaphores or barriers are used in order to prevent concurrent data

accesses.

Status: For the steppings affected, see the Summary Tables of Changes.

AR18. Code Segment Limit Violation May Occur On 4 Gigabyte Limit Check

Problem: Code Segment limit violation may occur on 4 Gigabyte limit check when the code

stream wraps around in a way that one instruction ends at the last byte of the

segment and the next instruction begins at 0x0.

Implication: This is a rare condition that may result in a system hang. Intel has not observed this

erratum with any commercially available software, or system.

Workaround: Avoid code that wraps around segment limit.

Status: For the steppings affected, see the Summary Tables of Changes.

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Intel LE80537VE001512 Datasheet Page 24