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DDR Data Swizzling
110 Datasheet, Volume 1
Table 9-1. DDR Data Swizzling
Table – Channel A
Land Name Land # MC Land Name
SA_DQ[0] AJ3 DQ06
SA_DQ[1] AJ4 DQ05
SA_DQ[2] AL3 DQ01
SA_DQ[3] AL4 DQ00
SA_DQ[4] AJ2 DQ04
SA_DQ[5] AJ1 DQ07
SA_DQ[6] AL2 DQ02
SA_DQ[7] AL1 DQ03
SA_DQ[8] AN1 DQ15
SA_DQ[9] AN4 DQ12
SA_DQ[10] AR3 DQ08
SA_DQ[11] AR4 DQ09
SA_DQ[12] AN2 DQ14
SA_DQ[13] AN3 DQ13
SA_DQ[14] AR2 DQ10
SA_DQ[15] AR1 DQ11
SA_DQ[16] AV2 DQ21
SA_DQ[17] AW3 DQ20
SA_DQ[18] AV5 DQ16
SA_DQ[19] AW5 DQ19
SA_DQ[20] AU2 DQ23
SA_DQ[21] AU3 DQ22
SA_DQ[22] AU5 DQ18
SA_DQ[23] AY5 DQ17
SA_DQ[24] AY7 DQ28
SA_DQ[25] AU7 DQ30
SA_DQ[26] AV9 DQ27
SA_DQ[27] AU9 DQ26
SA_DQ[28] AV7 DQ31
SA_DQ[29] AW7 DQ29
SA_DQ[30] AW9 DQ24
SA_DQ[31] AY9 DQ25
SA_DQ[32] AU35 DQ36
SA_DQ[33] AW37 DQ37
SA_DQ[34] AU39 DQ32
SA_DQ[35] AU36 DQ33
SA_DQ[36] AW35 DQ38
SA_DQ[37] AY36 DQ39
SA_DQ[38] AU38 DQ35
SA_DQ[39] AU37 DQ34
SA_DQ[40] AR40 DQ44
SA_DQ[41] AR37 DQ45
SA_DQ[42] AN38 DQ43
SA_DQ[43] AN37 DQ42
SA_DQ[44] AR39 DQ46
SA_DQ[45] AR38 DQ47
SA_DQ[46] AN39 DQ40
SA_DQ[47] AN40 DQ41
SA_DQ[48] AL40 DQ52
SA_DQ[49] AL37 DQ55
SA_DQ[50] AJ38 DQ51
SA_DQ[51] AJ37 DQ50
SA_DQ[52] AL39 DQ54
SA_DQ[53] AL38 DQ53
SA_DQ[54] AJ39 DQ48
SA_DQ[55] AJ40 DQ49
SA_DQ[56] AG40 DQ61
SA_DQ[57] AG37 DQ63
SA_DQ[58] AE38 DQ59
SA_DQ[59] AE37 DQ58
SA_DQ[60] AG39 DQ62
SA_DQ[61] AG38 DQ60
SA_DQ[62] AE39 DQ57
SA_DQ[63] AE40 DQ56
SA_DQ[64] AU12 DQ71
SA_DQ[65] AU14 DQ66
SA_DQ[66] AW13 DQ67
SA_DQ[67] AY13 DQ65
SA_DQ[68] AU13 DQ70
SA_DQ[69] AU11 DQ69
SA_DQ[70] AY12 DQ64
SA_DQ[71] AW12 DQ68
Table 9-1. DDR Data Swizzling
Table – Channel A
Land Name Land # MC Land Name
- Datasheet – Volume 1 of 2 1
- Contents 3
- Datasheet, Volume 1 4
- Datasheet, Volume 1 5 5
- Datasheet, Volume 1 7 7
- Revision History 8
- 1 Introduction 9
- Processor 10
- 1.1 Processor Feature Details 11
- 1.2 Interfaces 11
- 1.2.2 PCI Express* 12
- Datasheet, Volume 1 13 13
- Introduction 13
- 1.2.5 Processor Graphics 14
- 1.3 Power Management Support 15
- 1.4 Processor SKU Definitions 16
- 1.5 Package 17
- 1.6 Processor Compatibility 18
- 1.7 Terminology 19
- 1.8 Related Documents 22
- 2 Interfaces 23
- 2.1.3.1 Single-Channel Mode 25
- Flex Memory Technology Mode 25
- Interfaces 26
- 26 Datasheet, Volume 1 26
- 2.1.5.2 Command Overlap 27
- 2.2 PCI Express* Interface 28
- 2.2.1.1 Transaction Layer 29
- 2.2.1.2 Data Link Layer 29
- 2.2.1.3 Physical Layer 29
- 30 Datasheet, Volume 1 30
- 2.2.3 PCI Express* Port 31
- 2.3.1 DMI Error Flow 32
- 2.3.3 DMI Link Down 32
- Datasheet, Volume 1 33 33
- Interfaces 33
- 2.4.1.2 3D Pipeline 34
- 2.4.1.3 Video Engine 34
- 2.4.1.4 2D Engine 35
- 2.4.2.1 Display Planes 36
- 2.4.2.2 Display Pipes 37
- 2.4.2.3 Display Ports 37
- 2.6 Interface Clocking 38
- 3 Technologies 39
- Technologies 40
- 40 Datasheet, Volume 1 40
- Datasheet, Volume 1 41 41
- Technologies 41
- 42 Datasheet, Volume 1 42
- 3.4 Intel 43
- Turbo Boost Technology 43
- 3.5 Intel 44
- 3.7 Intel 45
- 64 Architecture x2APIC 45
- 46 Datasheet, Volume 1 46
- 4 Power Management 47
- (ACPI) States Supported 48
- 4.2.1 Enhanced Intel 50
- SpeedStep 50
- Technology 50
- 4.2.2 Low-Power Idle States 50
- C1 C1E C6C3 51
- 4.2.4.1 Core C0 State 52
- 4.2.4.2 Core C1 / C1E State 53
- 4.2.4.3 Core C3 State 53
- 4.2.4.4 Core C6 State 53
- 4.2.4.5 C-State Auto-Demotion 53
- 4.2.5 Package C-States 54
- 4.2.5.1 Package C0 55
- 4.2.5.2 Package C1/C1E 55
- 4.2.5.3 Package C3 State 56
- 4.2.5.4 Package C6 State 56
- Management 56
- Datasheet, Volume 1 57 57
- Power Management 57
- Power Management 58
- 58 Datasheet, Volume 1 58
- Datasheet, Volume 1 59 59
- 4.5 DMI Power Management 60
- 4.6 Graphics Power Management 60
- 4.6.4 Intel 61
- 4.6.5 Intel 61
- Graphics Dynamic Frequency 61
- 62 Datasheet, Volume 1 62
- 5 Thermal Management 63
- Thermal Management 64
- 64 Datasheet, Volume 1 64
- 6 Signal Description 65
- 6.5 Intel 69
- Flexible Display (Intel 69
- FDI) Interface 69
- 6.10 Power Sequencing Signals 72
- 6.11 Processor Power Signals 73
- 6.12 Sense Signals 73
- 7 Electrical Specifications 75
- Voltage Identification (VID) 76
- 7.5 System Agent (SA) V 80
- 7.7 Signal Groups 80
- 7.10 DC Specifications 84
- (Sheet 2 of 2) 85
- Specifications 86
- DC Specifications 90
- Electrical Specifications 92
- 92 Datasheet, Volume 1 92
- 8 Processor Land and Signal 93
- 94 Datasheet, Volume 1 94
- Land Name 100
- 108 Datasheet, Volume 1 108
- 9 DDR Data Swizzling 109
- Table – Channel A 110
- 112 Datasheet, Volume 1 112
- DDR Data Swizzling 112
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