Intel STRONGARM SA-1100 User Manual Page 165
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SA-1100 Developer’s Manual 11-15
Peripheral Control Module
0h B000 0070 DMA buffer A start address 3. DBSA3
0h B000 0074 DMA buffer A transfer count 3. DBTA3
0h B000 0078 DMA buffer B start address 3. DBSB3
0h B000 007C DMA buffer B transfer count 3. DBTB3
Channel 4 Registers
0h B000 0080 DMA device address register 4. DDAR4
0h B000 0084
DMA control/status register 4.
Write ones to set.
DCSR4
0h B000 0088 Write ones to clear.
0h B000 008C Read only.
0h B000 0090 DMA buffer A start address 4. DBSA4
0h B000 0094 DMA buffer A transfer count 4. DBTA4
0h B000 0098 DMA buffer B start address 4. DBSB4
0h B000 009C DMA buffer B transfer count 4. DBTB4
Channel 5 Registers
0h B000 00A0 DMA device address register 5. DDAR5
0h B000 00A4
DMA control/status register 5.
Write ones to set.
DCSR5
0h B000 00A8 Write ones to clear.
0h B000 00AC Read only.
0h B000 00B0 DMA buffer A start address 5. DBSA5
0h B000 00B4 DMA buffer A transfer count 5. DBTA5
0h B000 00B8 DMA buffer B start address 5. DBSB5
0h B000 00BC DMA buffer B transfer count 5. DBTB5
Physical Address Register Name Symbol
- StrongARM 1
- SA-1100 1
- Microprocessor 1
- SA-1100 Developer’s Manual 2
- Contents 3
- SA-1100 Developer’s Manual v 5
- SA-1100 Developer’s Manual ix 9
- SA-1100 Developer’s Manual xi 11
- SA-1100 Developer’s Manual xv 15
- Introduction 21
- 1.2 Overview 24
- Functional Description 29
- 2.2 Inputs/Outputs 31
- Implementation Options 37
- ARM™ Implementation Options 38
- Instruction Set 43
- Coprocessors 45
- ARM Architecture Reference 47
- 6.1.2.1 Software Icache Flush 55
- 6.1.3.1 Enabling the Icache 56
- 6.1.3.2 Disabling the Icache 56
- 6.2.1 Cacheable Bit – C 57
- 6.2.2 Bufferable Bit – B 57
- 6.2.3.1 Doubly Mapped Space 58
- 6.2.4.1 Enabling the Dcaches 59
- 6.2.4.2 Disabling the Dcaches 59
- 6.4 Read Buffer (RB) 60
- Memory-Management Unit (MMU) 63
- 8-2 SA-1100 68
- 8.4 Clocking During Test 70
- Register (GFER) 76
- Register (ICFP) 83
- 9.5.2.1 Entering Idle Mode 96
- 9.5.2.2 Exiting Idle Mode 97
- System Control Module 100
- 102
- • Sleep reset 111
- • Hardware reset 111
- • Software reset 111
- • Watchdog reset 111
- • Software reset 113
- • Sleep mode reset 113
- • DRAM Memory Interface 115
- • Static Memory Interface 116
- • PCMCIA Interface 116
- 10.1.1 Example Memory System 117
- 10.1.3 Reads 118
- 10.1.4 Writes 118
- 10.1.5 Transaction Summary 118
- 10.1.6 Read-Lock-Write 119
- 10-6 SA-1100 120
- Developer’s Manual 120
- 10-8 SA-1100 122
- 10-10 SA-1100 124
- 10-12 SA-1100 126
- 10.3.1 DRAM Overview 128
- 10.3.2 DRAM Timing 129
- 10-16 SA-1100 130
- A4778-01 131
- 10.4 Static Memory Interface 132
- 10.4.1 ROM Interface Overview 133
- 10-20 SA-1100 134
- A4782-01 135
- 10-22 SA-1100 136
- 10-24 SA-1100 138
- 10.6 PCMCIA Overview 140
- 10-28 SA-1100 142
- A6840-01 143
- A6844-01 144
- Socket x 145
- 10-32 SA-1100 146
- A4788-01 147
- 10-34 SA-1100 148
- Peripheral Control Module 151
- 11.7.1.2 Frame Buffer 168
- 11.7.1.3 Input FIFO 173
- 11.7.1.4 Lookup Palette 173
- 11.7.1.6 Output FIFO 174
- 11.7.1.7 LCD Controller Pins 175
- 11.7.3.1 LCD Enable (LEN) 176
- 11.8.1.1 Signalling Levels 207
- 11.8.1.2 Bit Encoding 208
- 11.8.1.3 Field Formats 209
- 11.8.1.4 Packet Formats 210
- 11.8.1.5 Transaction Formats 211
- 11.8.3 UDC Control Register 214
- 11.8.8.7 Bits 7..6 Reserved 221
- 11.8.9.7 Bits 7..6 Reserved 223
- 11.9.1.1 Bit Encoding 229
- 11.9.1.2 Frame Format 230
- 11.9.1.3 Address Field 230
- 11.9.1.4 Control Field 230
- 11.9.1.8 Receive Operation 232
- 11.9.1.9 Transmit Operation 233
- 11.9.3.3 Loopback Mode (LBM) 235
- 11.9.4.3 Receive Enable (RXE) 239
- 11.9.8 SDLC Status Register 0 246
- 11.9.9 SDLC Status Register 1 249
- 11.10.1.1 HP-SIR 254
- Modulation 254
- 11.10.1.2 UART Frame Format 254
- 11.10.2.1 4PPM Modulation 255
- 11.10.2.2 HSSP Frame Format 256
- 11.10.2.3 Address Field 257
- 11.10.2.4 Control Field 257
- 11.10.2.5 Data Field 257
- 11.10.2.6 CRC Field 257
- 11.10.2.8 Receive Operation 258
- 11.10.2.9 Transmit Operation 259
- 11.10.4.1 HP-SIR Enable (HSE) 261
- 11.10.6.2 Loopback Mode (LBM) 262
- 11.11.1.1 Frame Format 279
- 11.11.1.3 Receive Operation 279
- 11.11.1.4 Transmit Operation 280
- 11.11.3.1 Parity Enable (PE) 281
- 11.11.5.3 Break (BRK) 285
- 11.11.5.6 Loopback Mode (LBM) 286
- 11.12.1.1 Frame Format 297
- 11.12.5.1 MCP Data Register 0 309
- 11.12.5.2 MCP Data Register 1 310
- 11.12.5.3 MCP Data Register 2 311
- 11.12.7.1 Frame Format 319
- 11.12.9.2 Frame Format (FRF) 325
- 11.12.12 SSP Status Register 331
- DC Parameters 345
- AC Parameters 349
- Package and Pinout 355
- Debug Support 359
- Boundary-Scan Test Interface 361
- Register Summary A 371
- Register Summary 372
- B.1 Specifications 377
- B-2 SA-1110 378
- Cm Lm Rm 379
- C.1.1.1. Temperature Range 381
- C.1.1.2. Current Consumption 381
- C.1.1.3. Startup Time 381
- C-2 SA-1100 382
- C-4 SA-1100 384
- Internal Test D 385
- Internal Test 386
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