Intel STRONGARM SA-1100 User Manual

Intel® StrongARM® SA-1100 MicroprocessorDeveloper’s ManualAugust 1999Order Number: 278088-004

x SA-1100 Developer’s Manual11.9.1.5Data Field ... 11-8111.9.1.6CRC Field .

9-30 SA-1100 Developer’s Manual System Control ModuleAlso, the SA-1100 provides the power manager scratchpad register (PSPR) for saving any general

SA-1100 Developer’s Manual 9-31System Control ModuleFigure 9-3. Transitions Between Modes of OperationTable 9-2. SA-1100 Power and Clock Supply Sou

9-32 SA-1100 Developer’s Manual System Control Module9.5.6 Pin Operation in Sleep ModeThe SA-1100 pins are categorized by the following types based

SA-1100 Developer’s Manual 9-33System Control Module9.5.7 Power Manager RegistersThe power manager is controlled through eight 32-bit registers. The

9-34 SA-1100 Developer’s Manual System Control Module9.5.7.2 Power Manager General Configuration Register (PCFR)The PCFR contains bits used to confi

SA-1100 Developer’s Manual 9-35System Control Module9.5.7.3 Power Manager PLL Configuration Register (PPCR)The PPCR contains bits used to configure t

9-36 SA-1100 Developer’s Manual System Control Module9.5.7.4 Power Manager Wake-Up Enable Register (PWER)The following table shows the location of a

SA-1100 Developer’s Manual 9-37System Control Module9.5.7.5 Power Manager Sleep Status Register (PSSR)PSSR contains five status flags. The software s

9-38 SA-1100 Developer’s Manual System Control Module3DHDRAM control hold.This bit is set upon exit from sleep mode and indicates that the RAS<3:

SA-1100 Developer’s Manual 9-39System Control Module9.5.7.6 Power Manager Scratch Pad Register (PSPR)The power manager also contains a 32-bit registe

SA-1100 Developer’s Manual xi11.9.9.5Receive Transition Detect Status (RTD) (read/write, noninterruptible)...

9-40 SA-1100 Developer’s Manual System Control Module9.5.7.8 Power Manager Oscillator Status Register (POSR)The power manager oscillator status regi

SA-1100 Developer’s Manual 9-41System Control Module9.6 Reset ControllerThe reset controller manages the various reset sources within the SA-1100. Fr

9-42 SA-1100 Developer’s Manual System Control Module9.6.1 Reset Controller RegistersThe reset controller contains two registers, the reset controll

SA-1100 Developer’s Manual 9-43System Control Module9.6.1.2 Reset Controller Status Register (RCSR)The reset controller reset status register (RCSR)

SA-1100 Developer’s Manual 10-1Memory and PCMCIA Control Module10The external memory bus interface for the Intel® StrongARM® SA-1100 Microprocessor (

10-2 SA-1100 Developer’s ManualMemory and PCMCIA Control Module4 byte selects, nCAS<3:0>, 12 bits of multiplexed row and column addresses, nWE

SA-1100 Developer’s Manual 10-3Memory and PCMCIA Control Module10.1.1 Example Memory SystemFigure 10-2 shows a system using 1M x 16 DRAMs for a tota

10-4 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.1.2 Types of Memory AccessesThe SA-1100 performs memory accesses for the following

SA-1100 Developer’s Manual 10-5Memory and PCMCIA Control Module10.1.6 Read-Lock-WriteThe read-lock-write sequence is generated by an SWP instruction

xii SA-1100 Developer’s Manual11.10.10.4Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)...

10-6 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.2 Memory Configuration RegistersThe SA-1100 memory interface is programmed throug

SA-1100 Developer’s Manual 10-7Memory and PCMCIA Control Module10.2.1 DRAM Configuration Register (MDCNFG)MDCNFG is a read/write register and contain

10-8 SA-1100 Developer’s ManualMemory and PCMCIA Control Module31..17 DRI<14:0> DRAM refresh interval.The number of memory clock cycles (divid

SA-1100 Developer’s Manual 10-9Memory and PCMCIA Control Module10.2.2 DRAM CAS Waveform Shift Registers (MDCAS0, MDCAS1, MDCAS2)MDCAS0, MDCAS1, and M

10-10 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.2.3 Static Memory Control Registers (MSC1–0)MSC1 and MSC0 are read/write register

SA-1100 Developer’s Manual 10-11Memory and PCMCIA Control Module1 When SMCNFGx:RT=01, accesses to the selected bank will output a byte mask on nCAS&

10-12 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.2.4 Expansion Memory (PCMCIA) Configuration Register (MECR)MECR is a read/write r

SA-1100 Developer’s Manual 10-13Memory and PCMCIA Control ModuleTo calculate the recommended BS_xx value for each address space: divide the command w

10-14 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.3 Dynamic Interface OperationThis section describes the dynamic memory interface.

SA-1100 Developer’s Manual 10-15Memory and PCMCIA Control Module10.3.2 DRAM Timing The DRAM nCAS timing is generated using shift registers. The rate

SA-1100 Developer’s Manual xiii11.11.7.2Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)...

10-16 SA-1100 Developer’s ManualMemory and PCMCIA Control ModuleFigure 10-3 shows the rate of the shift registers during DRAM nCAS timing for a sing

SA-1100 Developer’s Manual 10-17Memory and PCMCIA Control ModuleFigure 10-4 shows the rate of the shift registers during DRAM nCAS timing for burst-o

10-18 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.3.3 DRAM RefreshThe SA-1100 provides support for CAS before RAS (CBR) refresh. Wh

SA-1100 Developer’s Manual 10-19Memory and PCMCIA Control ModuleThe RT fields in the MSCx registers specify the type of memory (burst-of-four ROM, bu

10-20 SA-1100 Developer’s ManualMemory and PCMCIA Control ModuleFigure 10-6. Burst-of-Eight ROM Timing DiagramA4780-01Memory ClockNote: One extra C

SA-1100 Developer’s Manual 10-21Memory and PCMCIA Control ModuleFigure 10-7. Eight Beat Burst Read from Burst-of-Four ROMFigure 10-8. Nonburst ROM,

10-22 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.4.3 SRAM Interface OverviewThe SA-1100 provides a 32-bit asynchronous SRAM interf

SA-1100 Developer’s Manual 10-23Memory and PCMCIA Control ModuleIn Figure 10-9, some of the parameters are defined as follows:tAS = Address setup to

10-24 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.4.6 FLASH EPROM Timing Diagrams and ParametersFlash reads have the same timing a

SA-1100 Developer’s Manual 10-25Memory and PCMCIA Control Module10.5 General Memory BUS TimingThis section explains the boundary cases between DRAM,

xiv SA-1100 Developer’s Manual11.12.6.1Audio Transmit FIFO Service Request Flag (ATS) (read-only, maskable interrupt)...

10-26 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.6 PCMCIA OverviewThe SA-1100 PCMCIA interface provides controls for one PCMCIA c

SA-1100 Developer’s Manual 10-27Memory and PCMCIA Control Module10.6.1 32-Bit Data Bus OperationThe SA-1100 PCMCIA interface supports the use of a 3

10-28 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.6.2 External Logic for PCMCIA ImplementationThe SA-1100 requires external logic

SA-1100 Developer’s Manual 10-29Memory and PCMCIA Control ModuleFigure 10-12. PCMCIA External Logic for a Two-Socket ConfigurationA6840-01D<15:0&g

10-30 SA-1100 Developer’s ManualMemory and PCMCIA Control ModuleFigure 10-13. PCMCIA External Logic for a One-Socket ConfigurationA6844-01D<15:0&

SA-1100 Developer’s Manual 10-31Memory and PCMCIA Control ModuleFigure 10-14. PCMCIA Voltage-Control LogicThe PCMCIA card voltage may be controlled t

10-32 SA-1100 Developer’s ManualMemory and PCMCIA Control ModuleFigure 10-15. PCMCIA Memory or I/O 16-Bit AccessA4788-01CPU ClockMemory ClockBS_xx+1

SA-1100 Developer’s Manual 10-33Memory and PCMCIA Control ModuleTiming parameters are in CPU clock cycle units. All are minimums except as noted:Addr

10-34 SA-1100 Developer’s ManualMemory and PCMCIA Control Module10.7 Initialization of the Memory InterfaceOn power-on reset, the dynamic memory int

SA-1100 Developer’s Manual 10-35Memory and PCMCIA Control ModuleThe following flow should be followed when coming out of reset, whether for sleep or

SA-1100 Developer’s Manual xv11.12.12.1Transmit FIFO Not Full Flag (TNF)(read-only, noninterruptible)...

SA-1100 Developer’s Manual 11-1Peripheral Control Module11This chapter describes the peripheral control units that are integrated within the Intel® S

11-2 SA-1100 Developer’s ManualPeripheral Control ModuleFigure 11-1. Peripheral Control Module Block Diagram11.2 Memory OrganizationSeveral of the

SA-1100 Developer’s Manual 11-3Peripheral Control ModuleTable 11-2 shows the base address for each of the peripheral control units. 1 The PPC does n

11-4 SA-1100 Developer’s ManualPeripheral Control Module11.3 InterruptsEach peripheral unit interfaces to the interrupt controller within the system

SA-1100 Developer’s Manual 11-5Peripheral Control Module11.4 Peripheral PinsEach peripheral has a number of dedicated pins with which to communicate

11-6 SA-1100 Developer’s ManualPeripheral Control Module11.5 Use of the GPIO Pins for Alternate FunctionsEach of the SA-1100’s six peripheral units

SA-1100 Developer’s Manual 11-7Peripheral Control Module11.6 DMA ControllerThe DMA controller consists of six independent DMA channels. Each channel

11-8 SA-1100 Developer’s ManualPeripheral Control Module11.6.1.1 DMA Device Address Register (DDARn)The DDARn is a 32-bit read/write register contai

SA-1100 Developer’s Manual 11-9Peripheral Control ModuleThe value written to the device select DS<3:0> field specifies which DMA request this c

xvi SA-1100 Developer’s Manual16.4 Instruction Register... 16

11-10 SA-1100 Developer’s ManualPeripheral Control Module Table 11-6. Valid Settings for the DDARn RegisterUnit Name FunctionDevice AddressDDA

SA-1100 Developer’s Manual 11-11Peripheral Control Module11.6.1.2 DMA Control/Status Register (DCSRn)The DCSRn is a 32-bit read/write register that c

11-12 SA-1100 Developer’s ManualPeripheral Control ModuleThe IE bit is the interrupt enable for the channel. An interrupt is generated if the DONEA,

SA-1100 Developer’s Manual 11-13Peripheral Control Module11.6.1.5 DMA Buffer B Start Address Register (DBSBn)The DBSBn is a 32-bit read/write registe

11-14 SA-1100 Developer’s ManualPeripheral Control Module11.6.3 DMA Register List The following table lists the registers contained within the DMA c

SA-1100 Developer’s Manual 11-15Peripheral Control Module0h B000 0070 DMA buffer A start address 3. DBSA30h B000 0074 DMA buffer A transfer count 3.

11-16 SA-1100 Developer’s ManualPeripheral Control Module11.7 LCD ControllerThe SA-1100’s LCD controller has three types of displays:Passive Color M

SA-1100 Developer’s Manual 11-17Peripheral Control ModuleWhen the LCD controller is disabled, control of its pins is given to the peripheral pin cont

11-18 SA-1100 Developer’s ManualPeripheral Control Module11.7.1 LCD Controller OperationThe LCD controller supports a variety of user-programmable o

SA-1100 Developer’s Manual 11-19Peripheral Control ModuleFigure 11-3. Palette Buffer Format.Individual Palette EntryBit1514131211109876543210ColorUn

SA-1100 Developer’s Manual xviiFigures1-1 SA-1100 Features...

11-20 SA-1100 Developer’s ManualPeripheral Control ModuleThe first palette entry (palette entry 0) also contains an extra field that is used to sync

SA-1100 Developer’s Manual 11-21Peripheral Control ModuleFigure 11-5. 8-Bits Per Pixel Data Memory Organization (Little Endian)Figure 11-6. 12-Bits

11-22 SA-1100 Developer’s ManualPeripheral Control ModuleIn dual-panel mode, pixels are presented to two halves of the screen at the same time (uppe

SA-1100 Developer’s Manual 11-23Peripheral Control Module11.7.1.3 Input FIFOData from the LCD’s DMA is directed either to the palette or the input FI

11-24 SA-1100 Developer’s ManualPeripheral Control Module11.7.1.5 Color/Gray-Scale DitheringFor passive displays, entries selected from the lookup p

SA-1100 Developer’s Manual 11-25Peripheral Control Module11.7.1.7 LCD Controller PinsPixel data is removed from the bottom of the output FIFO and is

11-26 SA-1100 Developer’s ManualPeripheral Control Module11.7.3 LCD Controller Control Register 0LCD controller control register 0 (LCCR0) contains

SA-1100 Developer’s Manual 11-27Peripheral Control Module Table 11-8 shows the LCD data pins and GPIO pins used for each mode of operation and the or

11-28 SA-1100 Developer’s ManualPeripheral Control ModuleFigure 11-8. LCD Data-Pin Pixel OrderingLDD<0> LDD<1> LDD<2> LDD<3>

SA-1100 Developer’s Manual 11-29Peripheral Control Module11.7.3.4 LCD Disable Done Interrupt Mask (LDM)The LCD disable done interrupt mask (LDM) bit

xviii SA-1100 Developer’s Manual11-24 HP-SIR Modulation Example... 11-10411-25 U

11-30 SA-1100 Developer’s ManualPeripheral Control ModuleThus two 16-bit values are packed into each word in the frame buffer. Each 16-bit value is

SA-1100 Developer’s Manual 11-31Peripheral Control Module11.7.3.8 Big/Little Endian Select (BLE)The big/little endian select (BLE) bit selects whethe

11-32 SA-1100 Developer’s ManualPeripheral Control ModuleThe following table shows the location of all 10 bit-fields located in LCD control register

SA-1100 Developer’s Manual 11-33Peripheral Control Module7PASPassive/active display select.0 – Passive or STN display operation enabled. Dither logic

11-34 SA-1100 Developer’s ManualPeripheral Control Module11.7.4 LCD Controller Control Register 1LCD controller control register 1 (LCCR1) contains

SA-1100 Developer’s Manual 11-35Peripheral Control Module11.7.4.4 Beginning-of-Line Pixel Clock Wait Count (BLW)The 8-bit beginning-of-line pixel clo

11-36 SA-1100 Developer’s ManualPeripheral Control Module11.7.5 LCD Controller Control Register 2LCD controller control register 2 (LCCR2) contains

SA-1100 Developer’s Manual 11-37Peripheral Control ModuleVSW does not affect generation of the frame clock signal in passive mode. Passive LCD displa

11-38 SA-1100 Developer’s ManualPeripheral Control ModuleThe following table shows the location of the four bit fields located in LCD control regist

SA-1100 Developer’s Manual 11-39Peripheral Control Module11.7.6 LCD Controller Control Register 3LCD controller control register 3 (LCCR3) contains s

SA-1100 Developer’s Manual xix10-5 DRAM Memory Size Options... 10-1410-6 DRAM R

11-40 SA-1100 Developer’s ManualPeripheral Control Module11.7.6.3 AC Bias Pin Transitions Per Interrupt (API)The 4-bit ac bias pin transitions per i

SA-1100 Developer’s Manual 11-41Peripheral Control Module11.7.6.7 Output Enable Polarity (OEP)The output enable polarity (OEP) bit is used to select

11-42 SA-1100 Developer’s ManualPeripheral Control Module11.7.7 LCD Controller DMA RegistersThe LCD controller has two fully independent DMA channel

SA-1100 Developer’s Manual 11-43Peripheral Control Module11.7.8 DMA Channel 1 Base Address RegisterDMA channel 1 base address register (DBAR1) is a 3

11-44 SA-1100 Developer’s ManualPeripheral Control Module11.7.9 DMA Channel 1 Current Address RegisterDMA channel 1 current address register (DCAR1)

SA-1100 Developer’s Manual 11-45Peripheral Control Module11.7.10 DMA Channel 2 Base and Current Address RegistersDMA channel 2’s base and current add

11-46 SA-1100 Developer’s ManualPeripheral Control Module11.7.11 LCD Controller Status RegisterThe LCD controller status register (LCSR) contains bi

SA-1100 Developer’s Manual 11-47Peripheral Control Module11.7.11.4 AC Bias Count Status (ABC) (read/write, nonmaskable interrupt)The ac bias count st

11-48 SA-1100 Developer’s ManualPeripheral Control Module11.7.11.10 Output FIFO Underrun Lower Panel Status (OUL) (read/write, maskable interrupt)Th

SA-1100 Developer’s Manual 11-49Peripheral Control Module2BERBus error status.0 – DMA has not attempted an access to reserved/nonexistent memory spac

SA-1100 Developer’s ManualInformation in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

11-50 SA-1100 Developer’s ManualPeripheral Control Module11.7.12 LCD Controller Register LocationsTable 11-9 shows the registers associated with the

SA-1100 Developer’s Manual 11-51Peripheral Control Module11.7.13 LCD Controller Pin Timing DiagramsFigure 11-10. Passive Mode Beginning-of-Frame Timi

11-52 SA-1100 Developer’s ManualPeripheral Control ModuleFigure 11-11. Passive Mode End-of-Frame TimingA4791-01L_FCLKL_LCLKL_PCLKLDD[x:0]Notes:BLW

SA-1100 Developer’s Manual 11-53Peripheral Control ModuleFigure 11-12. Passive Mode Pixel Clock and Data Pin TimingA4792-01L_FCLKL_LCLKL_PCLKLDD[3:0]

11-54 SA-1100 Developer’s ManualPeripheral Control ModuleFigure 11-13. Active Mode TimingA4793-01L_FCLK(VSYNC)L_LCLK(HSYNC)L_BIAS(OE)L_PCLKLDD[7:0]

SA-1100 Developer’s Manual 11-55Peripheral Control ModuleFigure 11-14. Active Mode Pixel Clock and Data Pin TimingA4794-01L_FCLK(VSYNC)L_BIASOE)L_LCL

11-56 SA-1100 Developer’s ManualPeripheral Control Module11.8 Serial Port 0 – USB Device ControllerThis section describes the implementation-specifi

SA-1100 Developer’s Manual 11-57Peripheral Control Module11.8.1.1 Signalling LevelsUSB uses differential signalling to encode data and to communicate

11-58 SA-1100 Developer’s ManualPeripheral Control Module11.8.1.2 Bit EncodingUSB uses nonreturn to zero inverted (NRZI) to encode individual bits.

SA-1100 Developer’s Manual 11-59Peripheral Control Module11.8.1.3 Field FormatsIndividual bits are assembled into groups called fields. Fields are us

SA-1100 SA-1100 Developer’s Manual 1-1Introduction11.1 Intel® StrongARM® SA-1100 MicroprocessorThe Intel® StrongARM® SA-1100 Microprocessor (SA-1100

11-60 SA-1100 Developer’s ManualPeripheral Control Module11.8.1.4 Packet FormatsUSB supports four packet types: token, data, handshake, and special.

SA-1100 Developer’s Manual 11-61Peripheral Control Module11.8.1.5 Transaction FormatsPackets are assembled into groups to form transactions. Four dif

11-62 SA-1100 Developer’s ManualPeripheral Control ModuleFigure 11-21. Control Transaction FormatsControl transfers are assembled by the host by fir

SA-1100 Developer’s Manual 11-63Peripheral Control ModuleTable 11-12 shows a summary of all device requests. Users should refer to the Universal Seri

11-64 SA-1100 Developer’s ManualPeripheral Control Module11.8.3 UDC Control RegisterThe UDC control register (UDCR) contains seven control bits: two

SA-1100 Developer’s Manual 11-65Peripheral Control Module11.8.3.7 Suspend/Resume Interrupt Mask (SRM)The suspend/resume interrupt mask (SRM) bit is u

11-66 SA-1100 Developer’s ManualPeripheral Control Module11.8.4 UDC Address RegisterThe UDC address register contains a 7-bit field that holds the d

SA-1100 Developer’s Manual 11-67Peripheral Control Module11.8.6 UDC IN Max Packet RegisterThe UDC IN max packet register holds the value of the numbe

11-68 SA-1100 Developer’s ManualPeripheral Control Module11.8.7 UDC Endpoint 0 Control/Status RegisterThe UDC endpoint zero control/status register

SA-1100 Developer’s Manual 11-69Peripheral Control Module11.8.7.8 Serviced Setup End (SSE)The serviced setup end bit will clear the SE bit (5) when w

1-2 SA-1100 Developer’s ManualIntroductionTable 1-1. Features of the SA-1100 CPU for AA and EA Parts• High Performance— 150 Dhrystone 2.1 MIPS @ 13

11-70 SA-1100 Developer’s ManualPeripheral Control Module11.8.8 UDC Endpoint 1 Control/Status RegisterThe UDC endpoint 1 control/status register con

SA-1100 Developer’s Manual 11-71Peripheral Control Module11.8.8.7 Bits 7..6 ReservedBits 7..6 are reserved for future use.Address: 0h 8000 0014 UDCCS

11-72 SA-1100 Developer’s ManualPeripheral Control Module11.8.9 UDC Endpoint 2 Control/Status RegisterThe UDC endpoint 2 control status register con

SA-1100 Developer’s Manual 11-73Peripheral Control Module11.8.9.7 Bits 7..6 ReservedBits 7..6 are reserved for future use.Address: 0h 8000 0018 UDCCS

11-74 SA-1100 Developer’s ManualPeripheral Control Module11.8.10 UDC Endpoint 0 Data RegisterThe UDC endpoint 0 data register is actually an 8-bit x

SA-1100 Developer’s Manual 11-75Peripheral Control Module11.8.12 UDC Data RegisterThe UDC data register (UDDR) is an 8-bit register corresponding to

11-76 SA-1100 Developer’s ManualPeripheral Control Module11.8.13 UDC Status/Interrupt RegisterThe UDC status/interrupt register (UDCSR) contains bit

SA-1100 Developer’s Manual 11-77Peripheral Control Module11.8.13.6 Reset Interrupt Request (RSTIR)The reset interrupt request register will be set i

11-78 SA-1100 Developer’s ManualPeripheral Control Module11.8.14 UDC Register LocationsTable 11-13 shows the registers associated with the UDC and t

SA-1100 Developer’s Manual 11-79Peripheral Control ModuleUsed as a UART, serial port 1 is identical to serial port 3. It supports most of the functio

SA-1100 Developer’s Manual 1-3IntroductionTable 1-3. Changes to the SA-1100 Core from the SA-110• Data cache reduced from 16 Kbyte to 8 Kbyte• Inter

11-80 SA-1100 Developer’s ManualPeripheral Control Module11.9.1.2 Frame FormatSDLC uses a flag (reserved bit pattern) to denote the beginning of a f

SA-1100 Developer’s Manual 11-81Peripheral Control Module11.9.1.5 Data FieldThe data field can be any length that is a multiple of 8 bits, including

11-82 SA-1100 Developer’s ManualPeripheral Control Module11.9.1.8 Receive OperationOnce the SDLC receiver is enabled, it enters hunt mode, searching

SA-1100 Developer’s Manual 11-83Peripheral Control ModuleIf the user disables the receiver during operation, reception of the current data byte is st

11-84 SA-1100 Developer’s ManualPeripheral Control Module11.9.1.11 Transmit and Receive FIFOsTo reduce chip size and power consumption, the SDLC’s F

SA-1100 Developer’s Manual 11-85Peripheral Control ModuleThe status registers contain bits that signal CRC, overrun, underrun, and receiver abort err

11-86 SA-1100 Developer’s ManualPeripheral Control Module11.9.3.4 Bit Modulation Select (BMS)The bit modulation select (BMS) bit selects whether the

SA-1100 Developer’s Manual 11-87Peripheral Control Module11.9.3.7 Receive Clock Edge Select (RCE)When sample clock operation is enabled (SCE=1), the

11-88 SA-1100 Developer’s ManualPeripheral Control Module11.9.4 SDLC Control Register 1SDLC control register 1 (SDCR1) contains eight bit fields tha

SA-1100 Developer’s Manual 11-89Peripheral Control Module11.9.4.2 Transmit Enable (TXE)The transmit enable (TXE) bit is used to enable and disable SD

1-4 SA-1100 Developer’s ManualIntroduction1.2 OverviewThe SA-1100 Microprocessor (SA-1100) is a general-purpose, 32-bit RISC microprocessor with a 1

11-90 SA-1100 Developer’s ManualPeripheral Control Module11.9.4.6 Address Match Enable (AME)The address match enable (AME) bit is used to enable or

SA-1100 Developer’s Manual 11-91Peripheral Control ModuleThe following table shows the location of the bits within SDLC control register 1. RXE and T

11-92 SA-1100 Developer’s ManualPeripheral Control Module11.9.5 SDLC Control Register 2SDLC control register 2 (SDCR2) contains the 8-bit address ma

SA-1100 Developer’s Manual 11-93Peripheral Control Module11.9.6 SDLC Control Registers 3 and 4SDLC control register 3 (SDCR3) contains the upper 4 bi

11-94 SA-1100 Developer’s ManualPeripheral Control Module11.9.7 SDLC Data RegisterThe SDLC data register (SDDR) is an 8-bit register corresponding t

SA-1100 Developer’s Manual 11-95Peripheral Control ModuleThe following table shows the bit locations corresponding to the data field and end-of-fram

11-96 SA-1100 Developer’s ManualPeripheral Control Module11.9.8 SDLC Status Register 0SDLC status register 0 (SDSR0) contains bits that signal the t

SA-1100 Developer’s Manual 11-97Peripheral Control Modulewhich indicates that the address, control, and data fields did not add up to an even multipl

11-98 SA-1100 Developer’s ManualPeripheral Control ModuleThe following table shows the bit locations corresponding to the status and flag bits withi

SA-1100 Developer’s Manual 11-99Peripheral Control Module11.9.9 SDLC Status Register 1SDLC status register 1 (SDSR1) contains flags and status bits t

SA-1100 Developer’s Manual 1-5IntroductionThe instruction set comprises eight basic instruction types:• Two make use of on-chip arithmetic logic unit

11-100 SA-1100 Developer’s ManualPeripheral Control Moduleregister. After the error in FIFO (EIF) status bit is set, the user should always read SDS

SA-1100 Developer’s Manual 11-101Peripheral Control ModuleThe following table shows the location of the flag and status bits within SDLC status regis

11-102 SA-1100 Developer’s ManualPeripheral Control Module11.9.10 UART Register LocationsTable 11-14 shows the registers associated with the UART an

SA-1100 Developer’s Manual 11-103Peripheral Control Module11.9.11 SDLC Register LocationsTable 11-15 shows the registers associated with the SDLC and

11-104 SA-1100 Developer’s ManualPeripheral Control Module11.10.1 Low-Speed ICP OperationFollowing reset, both the UART and HSSP are disabled, which

SA-1100 Developer’s Manual 11-105Peripheral Control ModuleFigure 11-25. UART Frame Format for IrDA Transmission (<= 115.2 Kbps)11.10.2 High-Speed

11-106 SA-1100 Developer’s ManualPeripheral Control Module11.10.2.2 HSSP Frame FormatWhen the 4-Mbps transmission rate is used, the high-speed seria

SA-1100 Developer’s Manual 11-107Peripheral Control Module11.10.2.3 Address FieldThe 8-bit address field is used by a transmitter to target a select

11-108 SA-1100 Developer’s ManualPeripheral Control Module11.10.2.7 Baud Rate GenerationThe baud rate is derived by dividing down a fixed 48-MHz clo

SA-1100 Developer’s Manual 11-109Peripheral Control ModuleWhen the receive FIFO is one- to two-thirds full, an interrupt or DMA transfer is signalled

1-6 SA-1100 Developer’s ManualIntroduction1.4 ARM™ ArchitectureThe SA-1100 implements the ARM V4 architecture as defined in the ARM Architecture Ref

11-110 SA-1100 Developer’s ManualPeripheral Control ModuleAt the end of each frame transmitted, the HSSP outputs a pulse called the serial infrared

SA-1100 Developer’s Manual 11-111Peripheral Control Moduleoperations. All reads and writes of the ICP by the CPU should be wordwide. Two separate, d

11-112 SA-1100 Developer’s ManualPeripheral Control Module11.10.5 HSSP Register DefinitionsThere are six registers within the HSSP: three control r

SA-1100 Developer’s Manual 11-113Peripheral Control Module11.10.6.3 Transmit FIFO Underrun Select (TUS)The transmit FIFO underrun select (TUS) bit is

11-114 SA-1100 Developer’s ManualPeripheral Control Moduletransmitting and receiving data at the same time; both are fully independent units. This f

SA-1100 Developer’s Manual 11-115Peripheral Control ModuleThe following table shows the location of the bits within HSSP control register 0. RXE and

11-116 SA-1100 Developer’s ManualPeripheral Control Module11.10.7 HSSP Control Register 1HSSP control register 1 (HSCR1) contains the 8-bit address

SA-1100 Developer’s Manual 11-117Peripheral Control Module11.10.8 HSSP Control Register 2The HSSP control register 2 (HSCR2) contains two bit-fields

11-118 SA-1100 Developer’s ManualPeripheral Control ModuleThe following table shows the location of the bits within HSSP control register 2. Both bi

SA-1100 Developer’s Manual 11-119Peripheral Control Module11.10.9 HSSP Data RegisterThe HSSP data register (HSDR) is an 8-bit register corresponding

SA-1100 Developer’s Manual 1-7Introduction1.4.6 Write BufferThe SA-1100 has an eight-entry write buffer with each entry able to contain 1 to 16 bytes

11-120 SA-1100 Developer’s ManualPeripheral Control ModuleThe following table shows the bit locations corresponding to the data field, end-of-frame

SA-1100 Developer’s Manual 11-121Peripheral Control Module11.10.10 HSSP Status Register 0HSSP status register 0 (HSSR0) contains bits that signal the

11-122 SA-1100 Developer’s ManualPeripheral Control Module11.10.10.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)The tra

SA-1100 Developer’s Manual 11-123Peripheral Control Module11.10.10.6 Framing Error Status (FRE) (read/write, nonmaskable interrupt)The framing error

11-124 SA-1100 Developer’s ManualPeripheral Control Module11.10.11 HSSP Status Register 1HSSP status register 1 (HSSR1) contains flags that indicate

SA-1100 Developer’s Manual 11-125Peripheral Control Module11.10.11.6 CRC Error Status (CRE) (read-only, noninterruptible)The CRC error flag (CRE) is

11-126 SA-1100 Developer’s ManualPeripheral Control ModuleThe following table shows the location of the flags within HSSP status register 1. The bit

SA-1100 Developer’s Manual 11-127Peripheral Control Module11.10.12 UART Register LocationsTable 11-16 shows the registers associated with the UART bl

11-128 SA-1100 Developer’s ManualPeripheral Control Module11.11 Serial Port 3 - UARTSerial port 3 is a general-purpose, full-duplex, universal async

SA-1100 Developer’s Manual 11-129Peripheral Control Module11.11.1.1 Frame FormatNRZ encoding is used by the UART to represent individual bit values.

11-130 SA-1100 Developer’s ManualPeripheral Control ModuleThe parity, framing, and overrun error bits are transferred down the receive FIFO along wi

SA-1100 Developer’s Manual 11-131Peripheral Control Moduleremoved from the receive FIFO without checking if more data is available. After this point,

11-132 SA-1100 Developer’s ManualPeripheral Control ModuleThe transmit logic sets or clears the parity bit to make the total number of ones transmit

SA-1100 Developer’s Manual 11-133Peripheral Control Module11.11.3.7 Transmit Clock Edge Select (TCE)When SCE=1, the transmit clock edge select (TCE)

11-134 SA-1100 Developer’s ManualPeripheral Control Module11.11.4 UART Control Registers 1 and 2UART control register 1 (UTCR1) contains the upper 4

SA-1100 Developer’s Manual 11-135Peripheral Control Module11.11.5 UART Control Register 3UART control register 3 (UTCR3) contains six different bit f

11-136 SA-1100 Developer’s ManualPeripheral Control Module11.11.5.5 Transmit FIFO Interrupt Enable (TIE)The transmit FIFO interrupt enable (TIE) bit

SA-1100 Developer’s Manual 11-137Peripheral Control Module11.11.6 UART Data RegisterThe UART data register (UTDR) is an 8-bit register corresponding

11-138 SA-1100 Developer’s ManualPeripheral Control ModuleThe following table shows the bit locations corresponding to the data field, parity, frami

SA-1100 Developer’s Manual 11-139Peripheral Control Module11.11.7 UART Status Register 0UART status register 0 (UTSR0) contains bits that signal the

SA-1100 Developer’s Manual 2-1Functional Description2This chapter provides a functional description of the Intel® StrongARM® SA-1100 Microprocessor (

11-140 SA-1100 Developer’s ManualPeripheral Control Module11.11.7.3 Receiver Idle Status (RID) (read/write, maskable interrupt)The receiver idle sta

SA-1100 Developer’s Manual 11-141Peripheral Control ModuleThe following table shows the bit locations corresponding to the status bits within UART st

11-142 SA-1100 Developer’s ManualPeripheral Control Module11.11.8 UART Status Register 1UART status register 1 (UTSR1) contains flags that indicate

SA-1100 Developer’s Manual 11-143Peripheral Control Module11.11.8.5 Framing Error Flag (FRE) (read-only, noninterruptible)The framing error status bi

11-144 SA-1100 Developer’s ManualPeripheral Control ModuleThe following table shows the bit locations corresponding to the flag bits within UART sta

SA-1100 Developer’s Manual 11-145Peripheral Control Module11.11.9 UART Register LocationsTable 11-18 shows the registers associated with serial port

11-146 SA-1100 Developer’s ManualPeripheral Control ModuleBoth the MCP and the off-chip codec contain programmable 7-bit divisors, one each for the

SA-1100 Developer’s Manual 11-147Peripheral Control Module11.12.1.1 Frame FormatEach MCP data frame is 128 bits long and is divided into two subframe

11-148 SA-1100 Developer’s ManualPeripheral Control ModuleNote that the transmit line is pulled low any time data is not being driven onto the pin.

SA-1100 Developer’s Manual 11-149Peripheral Control ModuleIf the input portion of the audio codec is enabled, when the counter reaches zero, a sample

SA-1100 Developer’s Manual iiiContents1 Introduction...

2-2 SA-1100 Developer’s ManualFunctional DescriptionFigure 2-1 shows the functional blocks contained in the SA-1100 integrated processor. Figure 2-2

11-150 SA-1100 Developer’s ManualPeripheral Control ModuleThe width of each entry within the audio and telecom FIFOs is 16 bits. However, the audio

SA-1100 Developer’s Manual 11-151Peripheral Control ModuleA register read is performed by writing a value to MCP data register 2 that contains the ad

11-152 SA-1100 Developer’s ManualPeripheral Control Module11.12.2 MCP Register DefinitionsThere are six registers within the MCP: two control regist

SA-1100 Developer’s Manual 11-153Peripheral Control ModuleOnce enabled, the MCP’s audio sample rate clock decrements at the programmed frequency with

11-154 SA-1100 Developer’s ManualPeripheral Control Module11.12.3.3 Multimedia Communications Port Enable (MCE)The MCP enable (MCE) bit is used to

SA-1100 Developer’s Manual 11-155Peripheral Control ModuleMCP within a receive data frame, the data valid bit is reset to zero for subsequent data fr

11-156 SA-1100 Developer’s ManualPeripheral Control Module11.12.3.10 Loopback Mode (LBM)The loopback mode (LBM) bit is used to enable and disable th

SA-1100 Developer’s Manual 11-157Peripheral Control Module16 MCE Multimedia communications port enable.0 – MCP operation disabled, control of the TXD

11-158 SA-1100 Developer’s ManualPeripheral Control Module11.12.4 MCP Control Register 1The MCP control register 1 (MCCR1) contains one bit that sel

SA-1100 Developer’s Manual 11-159Peripheral Control Module11.12.5.1 MCP Data Register 0When MCP data register 0 (MCDR0) is read, the bottom entry of

SA-1100 Developer’s Manual 2-3Functional Description2.2 Inputs/OutputsFigure 2-2. SA-1100 Functional DiagramA6975-01Intel®StrongARM®*SA-1100[208-pin

11-160 SA-1100 Developer’s ManualPeripheral Control Module11.12.5.2 MCP Data Register 1When MCP data register 1 (MCDR1) is read, the bottom entry of

SA-1100 Developer’s Manual 11-161Peripheral Control Module11.12.5.3 MCP Data Register 2MCDR2 contains 21 bits and is used to perform reads and writes

11-162 SA-1100 Developer’s ManualPeripheral Control ModuleThe following table shows the location of MCP data register 2. Note that the reset state o

SA-1100 Developer’s Manual 11-163Peripheral Control Module11.12.6 MCP Status RegisterThe MCP status register (MCSR) contains bits that signal FIFO ov

11-164 SA-1100 Developer’s ManualPeripheral Control Module11.12.6.3 Telecom Transmit FIFO Service Request Flag (TTS) (read-only, maskable interrupt)

SA-1100 Developer’s Manual 11-165Peripheral Control Module11.12.6.7 Telecom Transmit FIFO Underrun Status (TTU) (read/write, nonmaskable interrupt)Th

11-166 SA-1100 Developer’s ManualPeripheral Control Module11.12.6.12 Telecom Receive FIFO Not Empty Flag (TNE) (read-only, noninterruptible)The tele

SA-1100 Developer’s Manual 11-167Peripheral Control ModuleThe following table shows the bit locations corresponding to the status and flag bits withi

11-168 SA-1100 Developer’s ManualPeripheral Control Module6 TTU Telecom transmit FIFO underrun.0 – Telecom transmit FIFO has not experienced an unde

SA-1100 Developer’s Manual 11-169Peripheral Control Module11.12.7 SSP OperationFollowing reset, both the MCP and SSP logic within serial port 4 is di

2-4 SA-1100 Developer’s ManualFunctional Description2.3 Signal DescriptionThe following table describes the signals.Key to Signal Types: n – Active

11-170 SA-1100 Developer’s ManualPeripheral Control ModuleFigure 11-35 shows the Texas Instruments* synchronous serial frame format for a single tra

SA-1100 Developer’s Manual 11-171Peripheral Control ModuleFigure 11-36 shows one of the four possible configurations for the Motorola* SPI frame form

11-172 SA-1100 Developer’s ManualPeripheral Control ModuleFigure 11-37 shows the National Microwire* frame format for a single transmitted frame and

SA-1100 Developer’s Manual 11-173Peripheral Control Module11.12.7.2 Baud Rate GenerationThe baud or bit rate is derived by dividing down the 3.6864-M

11-174 SA-1100 Developer’s ManualPeripheral Control Module11.12.7.4 CPU and DMA Register Access SizesBit positioning, byte ordering, and addressing

SA-1100 Developer’s Manual 11-175Peripheral Control Module11.12.9.1 Data Size Select (DSS)The 4-bit data size select (DSS) field is used to select th

11-176 SA-1100 Developer’s ManualPeripheral Control Module11.12.9.4 Serial Clock Rate (SCR)The 8-bit serial clock rate (SCR) bit field is used to se

SA-1100 Developer’s Manual 11-177Peripheral Control Module11.12.10 SSP Control Register 1The SSP control register 1 (SSCR1) contains six different bi

11-178 SA-1100 Developer’s ManualPeripheral Control Module11.12.10.5 Serial Clock Phase (SPH)The serial clock phase (SPH) bit selects the phase rela

SA-1100 Developer’s Manual 11-179Peripheral Control Module11.12.10.6 External Clock Select (ECS)The external clock select (ECS) bit selects whether t

SA-1100 Developer’s Manual 2-5Functional DescriptionL_FCLK OCZ LCD frame clock.L_LCLK OCZ LCD line clock.L_PCLK OCZ LCD pixel clock.L_BIAS OCZ LCD ac

11-180 SA-1100 Developer’s ManualPeripheral Control Module11.12.11 SSP Data Register The SSP data register (SSDR) is 16 bits wide and corresponds to

SA-1100 Developer’s Manual 11-181Peripheral Control Module11.12.12 SSP Status RegisterThe SSP status register (SSSR) contains bits that signal overru

11-182 SA-1100 Developer’s ManualPeripheral Control Module11.12.12.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)The rece

SA-1100 Developer’s Manual 11-183Peripheral Control Module11.12.13 MCP Register LocationsTable 11-19 shows the registers associated with the MCP and

11-184 SA-1100 Developer’s ManualPeripheral Control Module11.13 Peripheral Pin Controller (PPC)The peripheral pin controller (PPC) takes individual

SA-1100 Developer’s Manual 11-185Peripheral Control ModuleSerial port 1 and serial port 4 both contain two serial-to-parallel engines that operate in

11-186 SA-1100 Developer’s ManualPeripheral Control ModuleBit Name Description7..0 LDD<7:0>LCD data pin direction.0 – If LCD controller disabl

SA-1100 Developer’s Manual 11-187Peripheral Control Module11.13.4 PPC Pin State RegisterPin state is both monitored and controlled by reading/writing

11-188 SA-1100 Developer’s ManualPeripheral Control ModuleBit Name Description7..0 LDD<7:0>LCD data pin state.Read – Current state of LCD data

SA-1100 Developer’s Manual 11-189Peripheral Control Module11.13.5 PPC Pin Assignment RegisterThe UART in serial port 1 and the SSP in serial port 4 c

2-6 SA-1100 Developer’s ManualFunctional DescriptionnRESET_OUT OCZ Reset out. This signal is asserted when nRESET is asserted and deasserts when the

11-190 SA-1100 Developer’s ManualPeripheral Control Module11.13.6 PPC Sleep Mode Pin Direction RegisterWhen sleep mode is entered, reset is asserted

SA-1100 Developer’s Manual 11-191Peripheral Control ModuleBit Name Description7..0 LDD<7:0>LCD data sleep mode pin direction.0 – LCD data pin c

11-192 SA-1100 Developer’s ManualPeripheral Control Module11.13.7 PPC Pin Flag RegisterThe PPC pin flag register (PPFR) is used to determine which p

SA-1100 Developer’s Manual 11-193Peripheral Control Module11.13.8 PPC Register LocationsTable 11-21 shows the registers associated with the PPC and t

SA-1100 Developer’s Manual 12-1DC Parameters12This chapter defines the dc parameters for the Intel® StrongARM® SA-1100 Microprocessor (SA-1100).12.1

12-2 SA-1100 Developer’s ManualDC Parameters12.2 DC Operating ConditionsTable 12-2 lists the functional operating dc parameters for the SA-1100. Ta

SA-1100 Developer’s Manual 12-3DC Parameters12.3 Power Supply Voltages and CurrentsTable 12-3 specifies the power supply voltages and currents for th

SA-1100 Developer’s Manual 13-1AC Parameters13This chapter defines the ac parameters for the Intel® StrongARM® SA-1100 Microprocessor (SA-1100).13.1

SA-1100 Developer’s Manual 2-7Functional Description2.4 Memory MapFigure 2-3 shows the SA-1100 memory map. The map is divided into four main partitio

13-2 SA-1100 Developer’s ManualAC Parameters13.2 Module ConsiderationsThe edge rates for the SA-1100 processor are such that the lumped load model p

SA-1100 Developer’s Manual 13-3AC Parameters13.4 LCD Controller SignalsFigure 13-2 describes the LCD timing parameters. The LCD pin timing specificat

13-4 SA-1100 Developer’s ManualAC Parameters13.6 Timing ParametersTable 13-2 lists the ac timing parameters for the SA-1100 for AA and BA parts. For

SA-1100 Developer’s Manual 13-5AC Parameters13.6.1 Asynchronous Signal Timing DescriptionsnPWAIT is an input and is received through a synchronizer.

SA-1100 Developer’s Manual 14-1Package and Pinout1414.1 Mechanical Data and Packaging InformationFigure 14-1 shows the SA-1100 208-pin LQFP mechanica

14-2 SA-1100 Developer’s ManualPackage and PinoutNote: All VDDX1, VDDX2, and VDDX3 pins should be connected directly to the VDDX power plane of the

SA-1100 Developer’s Manual 14-3Package and Pinout14.2 Mini-Ball Grid Array – (mBGA)Figure 14-2 shows the SA-1100 256 mini-ball grid array (mBGA) mech

14-4 SA-1100 Developer’s ManualPackage and PinoutNote: All VDDX1, VDDX2, and VDDX3 pins should be connected directly to the VDDX power plane of the

SA-1100 Developer’s Manual 15-1Debug Support15Due to the integration level of the Intel® StrongARM® SA-1100 Microprocessor (SA-1100), many functions

2-8 SA-1100 Developer’s ManualFunctional DescriptionFigure 2-3. SA-1100 Memory Map0h0000 0000512 MbyteStatic Memory Internal RegistersPCMCIA Interf

SA-1100 Developer’s Manual 16-1Boundary-Scan Test Interface16The boundary-scan interface conforms to the IEEE Std. 1149.1 – 1990, Standard Test Acces

16-2 SA-1100 Developer’s ManualBoundary-Scan Test Interface16.2 ResetThe boundary-scan interface includes a state-machine controller (the TAP contro

SA-1100 Developer’s Manual 16-3Boundary-Scan Test Interface16.5.1 EXTEST (00000)The boundary-scan (BS) register is placed in test mode by the EXTEST

16-4 SA-1100 Developer’s ManualBoundary-Scan Test Interface16.5.4 HIGHZ (00101)The HIGHZ instruction connects a 1-bit shift register (the BYPASS reg

SA-1100 Developer’s Manual 16-5Boundary-Scan Test Interface16.6 Test Data RegistersFigure 16-2 illustrates the structure of the boundary-scan logic.

16-6 SA-1100 Developer’s ManualBoundary-Scan Test Interface16.6.2 SA-1100 Device Identification (ID) Code Register Purpose: This register is used to

SA-1100 Developer’s Manual 16-7Boundary-Scan Test Interface16.7 Boundary-Scan Interface SignalsFigure 16-3. Boundary-Scan General TimingA4772-01tckD

16-8 SA-1100 Developer’s ManualBoundary-Scan Test InterfaceFigure 16-4. Boundary-Scan Tristate TimingFigure 16-5. Boundary-Scan Reset Timing A4773

SA-1100 Developer’s Manual 16-9Boundary-Scan Test InterfaceTable 16-1 shows the SA-1100 boundary-scan interface timing specifications. Tab

SA-1100 Developer’s Manual 3-1ARM™ Implementation Options3The following sections describe ARM™ architecture options that are implemented by the Intel

SA-1100 Developer’s Manual A-1Register Summary AThis appendix describes all of the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) internal regist

A-2 SA-1100 Developer’s ManualRegister SummaryPower Manager Registers0h 9002 0000 PMCR Power manager control register.0h 9002 0004 PSSR Power manage

SA-1100 Developer’s Manual A-3Register Summary0h B000 0044DCSR2DMA control/status register 2 – write ones to set.0h B000 0048 Write ones to clear.0h

A-4 SA-1100 Developer’s ManualRegister SummaryLCD Controller Registers0hB010 0000 LCCR0 LCD controller control register 0.0hB010 0004 LCSR LCD contr

SA-1100 Developer’s Manual A-5Register SummarySDLC Registers (Serial Port 1)0h 8002 0060 SDCR0 SDLC control register 0.0h 8002 0064 SDCR1 SDLC contro

A-6 SA-1100 Developer’s ManualRegister SummaryUART Registers (Serial Port 3)0h 8005 0000 UTCR0 UART control register 0.0h 8005 0004 UTCR1 UART contr

SA-1110 Developer’s Manual B-13.6864–MHz Oscillator Specifications BA 3.6864-MHz crystal oscillator is integrated on the Intel® StrongARM® SA-1100 Mi

B-2 SA-1110 Developer’s Manual3.6864–MHz Oscillator Specificationsapproximately twice the values given, the startup time in this situation will be a

SA-1110 Developer’s Manual B-33.6864–MHz Oscillator SpecificationsB.1.2 Quartz Crystal SpecificationThe following specifications for the quartz cryst

3-2 SA-1100 Developer’s ManualARM™ Implementation Optionstransfer the whole 32-bit value, and not just the flag or control fields. When multiple exc

SA-1100 Developer’s Manual C-132.768–kHz Oscillator Specifications CA 32.768-kHz crystal oscillator is integrated on the Intel® StrongARM® SA-1100 Mi

C-2 SA-1100 Developer’s Manual32.768–kHz Oscillator Specificationsapproximately twice the values given; the startup time in this situation will be a

SA-1100 Developer’s Manual C-332.768–kHz Oscillator SpecificationsC.1.2 Quartz Crystal SpecificationThe following specifications for the quartz cryst

C-4 SA-1100 Developer’s Manual32.768–kHz Oscillator SpecificationsThe following values are not required for the crystal oscillator to function, but

SA-1100 Developer’s Manual D-1Internal TestInternal Test DThe Test Unit contains a register that enables certain test modes. Some of these test modes

D-2 SA-1100 Developer’s ManualInternal Test27..28 Reserved —29..31 TSEL2-0 Test selects. Routes internal signals out onto GPIO<27> for observi

Support, Products, and DocumentationIf you need general information or support, call 1-800-628-8686 or visit Intel’s website at:http://www.intel.comCo

SA-1100 Developer’s Manual 3-3ARM™ Implementation Options3.2.3 AbortAn abort can be signalled by the internal memory-management unit, through a data

iv SA-1100 Developer’s Manual5.2.11 Registers 10 – 12 RESERVED... 5-65.2.12 Register 13 –

3-4 SA-1100 Developer’s ManualARM™ Implementation Options3.2.4 Vector SummaryTable 3-1 lists byte addresses, and they normally contain branch instru

SA-1100 Developer’s Manual 3-5ARM™ Implementation Options3.2.6 Interrupt Latencies and Enable TimingThe ability to recognize an IRQ or FIQ interrupt

SA-1100 Developer’s Manual 4-1Instruction Set4This section describes the instruction timing for the Intel® StrongARM® SA-1100 Microprocessor (SA-1100

SA-1100 Developer’s Manual 5-1Coprocessors 5The operation and configuration of the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) is controlled w

5-2 SA-1100 Developer’s ManualCoprocessors5.2 Coprocessor 15 DefinitionThe SA-1100 coprocessor 15 contains registers that control the cache, MMU, an

SA-1100 Developer’s Manual 5-3Coprocessors5.2.2 Register 1 – ControlRegister 1 is a read/write register containing control bits. All writable bits in

5-4 SA-1100 Developer’s ManualCoprocessors5.2.3 Register 2 – Translation Table BaseRegister 2 is a read/write register that holds the base of the c

SA-1100 Developer’s Manual 5-5Coprocessors5.2.8 Register 7 – Cache Control OperationsRegister 7 is a write-only register. The CRm and OPC_2 fields ar

SA-1100 Developer’s Manual v9 System Control Module...

5-6 SA-1100 Developer’s ManualCoprocessors5.2.10 Register 9 – Read-Buffer OperationsThe read buffer is controlled and accessed through register 9 of

SA-1100 Developer’s Manual 5-7Coprocessors5.2.12 Register 13 – Process ID Virtual Address MappingThe SA-1100 supports the remapping of virtual addres

5-8 SA-1100 Developer’s ManualCoprocessors5.2.13 Register 14 – Debug Support (Breakpoints)The SA-1100 supports address and data breakpoints through

SA-1100 Developer’s Manual 5-9Coprocessors5.2.14 Register 15 – Test, Clock, and Idle ControlRegister 15 is a write-only register. The CRm and OPC_2 f

SA-1100 Developer’s Manual 6-1Caches, Write Buffer, and Read Buffer6To reduce effective memory access time, the Intel® StrongARM® SA-1100 Microproces

6-2 SA-1100 Developer’s ManualCaches, Write Buffer, and Read Buffer6.1.3 Icache Enable/Disable and ResetThe Icache is automatically disabled and flu

SA-1100 Developer’s Manual 6-3Caches, Write Buffer, and Read Buffermemory-management page table. For this reason, in order to use the Dcaches, the MM

6-4 SA-1100 Developer’s ManualCaches, Write Buffer, and Read Buffer6.2.3 Software Dcache FlushThe SA-1100 supports the flush and clean operations on

SA-1100 Developer’s Manual 6-5Caches, Write Buffer, and Read Buffer6.2.4.1 Enabling the DcachesTo enable the Dcaches, make sure that the MMU is enabl

vi SA-1100 Developer’s Manual9.5.3.6 Booting After Sleep Mode... 9-299.5.3.7 Reviving the DRAMs f

6-6 SA-1100 Developer’s ManualCaches, Write Buffer, and Read Buffer6.3.2.2 Writes to a Bufferable and Noncacheable Location (B=1,C=0)If the write bu

SA-1100 Developer’s Manual 6-7Caches, Write Buffer, and Read BufferAny two data words with the same virtual address may not be contained in the RB at

SA-1100 Developer’s Manual 7-1Memory-Management Unit (MMU)7This chapter describes the memory-management functions.7.1 Overview The Intel® StrongARM®

7-2 SA-1100 Developer’s ManualMemory-Management Unit (MMU)7.3.1 Cacheable Reads (Linefetches)A linefetch can be safely aborted on any word in the tr

SA-1100 Developer’s Manual 7-3Memory-Management Unit (MMU)Note: Care must be taken if the translated address differs from the untranslated address be

SA-1100 Developer’s Manual 8-1Clocks8This section describes the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) clocks. The following diagram show

8-2 SA-1100 Developer’s ManualClocks8.2 Core Clock Configuration RegisterThe core clock frequency is configured by software through the core clock c

SA-1100 Developer’s Manual 8-3Clocks8.3 Driving SA-1100 Crystal Pins from an External SourceIn most applications, a 3.6864-MHz crystal will be connec

SA-1100 Developer’s Manual vii10.5.3 DRAM Access Followed by a Refresh Operation... 10-2510.6 PCMCIA Overview...

8-4 SA-1100 Developer’s ManualClocksIf the PXTAL or TXTAL pin is driven above the voltage indicated, there will be no permanent damage to the proces

SA-1100 Developer’s Manual 9-1System Control Module9This chapter describes the system control module that controls several processor-wide system func

9-2 SA-1100 Developer’s Manual System Control Module9.1.1 GPIO Register DefinitionsThere are a total of eight registers within the GPIO control bloc

SA-1100 Developer’s Manual 9-3System Control Module9.1.1.1 GPIO Pin-Level Register (GPLR)The state of each of the GPIO port pins is visible through t

9-4 SA-1100 Developer’s Manual System Control Module9.1.1.2 GPIO Pin Direction Register (GPDR)Pin direction is controlled by programming the GPIO pi

SA-1100 Developer’s Manual 9-5System Control Module9.1.1.3 GPIO Pin Output Set Register (GPSR) and Pin Output Clear Register (GPCR)When a port is con

9-6 SA-1100 Developer’s Manual System Control Module9.1.1.4 GPIO Rising-Edge Detect Register (GRER) and Falling-Edge Detect Register (GFER)Each GPIO

SA-1100 Developer’s Manual 9-7System Control Module9.1.1.5 GPIO Edge Detect Status Register (GEDR)The GPIO edge detect status register (GEDR) contain

9-8 SA-1100 Developer’s Manual System Control Module9.1.1.6 GPIO Alternate Function Register (GAFR)The GPIO alternate function register (GAFR) conta

SA-1100 Developer’s Manual 9-9System Control Module9.1.2 GPIO Alternate FunctionsMost GPIO pins have an alternate function that can be invoked to ena

viii SA-1100 Developer’s Manual11.7.5.1Lines Per Panel (LPP) ... 11-3611.7.5.2Vertical Sync Pu

9-10 SA-1100 Developer’s Manual System Control Module9.1.3 GPIO Register LocationsThe following table shows the registers associated with the GPIO b

SA-1100 Developer’s Manual 9-11System Control Module9.2 Interrupt ControllerThe SA-1100 interrupt controller provides masking capability for all inte

9-12 SA-1100 Developer’s Manual System Control Module9.2.1.1 Interrupt Controller Pending Register (ICPR)The ICPR is a 32-bit read-only register tha

SA-1100 Developer’s Manual 9-13System Control Module9.2.1.2 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Register (ICFP)The ICIP

9-14 SA-1100 Developer’s Manual System Control Module9.2.1.3 Interrupt Controller Mask Register (ICMR)The interrupt controller mask register (ICMR)

SA-1100 Developer’s Manual 9-15System Control Module9.2.1.4 Interrupt Controller Level Register (ICLR)The interrupt controller level register (ICLR)

9-16 SA-1100 Developer’s Manual System Control Module9.2.1.5 Interrupt Controller Control Register (ICCR)The interrupt controller control register (

SA-1100 Developer’s Manual 9-17System Control Module9.2.2 Interrupt Controller Register LocationsThe following table shows the registers associated w

9-18 SA-1100 Developer’s Manual System Control Module9.3.2 RTC Alarm Register (RTAR)The real-time clock alarm register is a 32-bit register that is

SA-1100 Developer’s Manual 9-19System Control Module9.3.4 RTC Trim Register (RTTR)The RTTR is programmed by the user to select the frequency of the 1

SA-1100 Developer’s Manual ix11.8.3.1UDC Disable (UDD)... 11-6411.8.3.2 UDC Active (UDA) ..

9-20 SA-1100 Developer’s Manual System Control Module9.3.5.2 RTTR Value CalculationsAfter the true frequency of the oscillator is known, it must be

SA-1100 Developer’s Manual 9-21System Control ModuleThis trim setting leaves an error of .16 cycles per 1023 seconds. The error calculation yields (i

9-22 SA-1100 Developer’s Manual System Control Module9.4.1 OS Timer Count Register (OSCR)The OS timer count register is a 32-bit counter that increm

SA-1100 Developer’s Manual 9-23System Control Module9.4.4 OS Timer Status Register (OSSR)This status register contains status bits indicating whether

9-24 SA-1100 Developer’s Manual System Control Module9.4.5 OS Timer Interrupt Enable Register (OIER)This register contains four enable bits indicati

SA-1100 Developer’s Manual 9-25System Control Module9.4.7 OS Timer Register LocationsTable 9-1 shows the registers associated with the OS timer and t

9-26 SA-1100 Developer’s Manual System Control Module9.5 Power ManagerThe SA-1100 contains power management logic that controls the transition betw

SA-1100 Developer’s Manual 9-27System Control Module9.5.2.2 Exiting Idle ModeAny enabled interrupt from the system unit or peripheral unit will cause

9-28 SA-1100 Developer’s Manual System Control Module9.5.3.3 The Sleep Shutdown SequenceThe sleep state machine begins the shutdown sequence. This s

SA-1100 Developer’s Manual 9-29System Control Module• In the first step of the wake-up sequence, the following actions occur:a. The PWR_EN pin is ass