Intel CONTROLLERS 413808 User Manual download pdf (Page 13)

3.1.2.1 SRAM Memory Array Space .............................................514
3.1.2.2 Memory-Mapped Register Space......................................514
3.1.2.3 North Internal Bus Port Address Decode ..........................514
3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ) .....514
3.1.5.1 SRAM State Machine and Pipeline Queues......................514
3.1.5.2 Error Correction Logic .......................................................515

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Intel CONTROLLERS 413808 User Manual Page 13

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