Intel UPI-C42 User Manual

*Other brands and names are the property of their respective owners.Information in this document is provided in connection with Intel products. Intel

UPI-C42/UPI-L42290414–14Figure 6. Quick-Pulse Programming AlgorithmQuick-Pulse Programming AlgorithmAs previously stated, the UPI-C42 will be pro-gram

UPI-C42/UPI-L42b. Apply access code to appropriate inputs to putthe device into security mode.c. Apply high voltage to EA and VDDpins.d. Follow the pr

UPI-C42/UPI-L42Table 3. Signature Mode TableAddressDevice No. ofType BytesTest Code/Checksum 0 0FH ROM/OTP 2516H 1EHIntel Signature 10H 11H ROM/OTP 2U

UPI-C42/UPI-L42SYNC MODE TIMING DIAGRAMS290414–15Minimum SpecificationsSYNC Operation Time, tSYNCe3.5 XTAL 2 Clock cycles. Reset Time, tRSe4tCY.NOTE:T

UPI-C42/UPI-L42APPLICATIONS (Continued)290414–10Figure 9. 8048H-UPI-C42 Interface290414–11Figure 10. UPI-C42-8243 Keyboard Scanner290414–13Figure 11.

UPI-C42/UPI-L42ABSOLUTE MAXIMUM RATINGS*Ambient Temperature Under Bias ÀÀÀÀ0§Ctoa70§CStorage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa150§CVoltage on Any Pin wit

UPI-C42/UPI-L42DC CHARACTERISTICSTAe0§Ctoa70§C, VCCeVDDea5Vg10%;a3.3Vg10% UPI-L42 (Continued)Symbol ParameterUPI-C42 UPI-L42Units NotesMin Max Min Max

UPI-C42/UPI-L42AC CHARACTERISTICSTAe0§Ctoa70§C, VSSe0V, VCCeVDDea5Vg10%;a3.3Vg10% for the UPI-L42NOTE:All AC Characteristics apply to both the UPI-C42

UPI-C42/UPI-L42AC CHARACTERISTICSTAe0§Ctoa70§C, VSSe0V, VCCeVDDea5Vg10%;a3.3Vg10% for the UPI-L42 (Continued)CLOCKSymbol Parameter Min Max UnitstCYUPI

UPI-C42/UPI-L42AC CHARACTERISTICSÐPROGRAMMING (UPI-C42 AND UPI-L42)TAe25§Cg5§C, VCCe6.25Vg0.25V, VDDLea5Vg0.25V, VDDHe12.75Vg0.25V(87C42/87L42 ONLY)Sy

UPI-C42/UPI-L42Table 1. Pin DescriptionDIP PLCC QFPSymbol Pin Pin Pin Type Name and FunctionNo. No. No.TEST 0, 1 2 18 I TEST INPUTS: Input pins which

UPI-C42/UPI-L42DRIVING FROM AN EXTERNAL SOURCE290414–18NOTE:See XTAL1 Configuration Table.290414–19Rise and Fall Times Should NotExceed 10 ns. Resisto

UPI-C42/UPI-L42WAVEFORMSREAD OPERATIONÐDATA BUS BUFFER REGISTER290414–22WRITE OPERATIONÐDATA BUS BUFFER REGISTER290414–23CLOCK TIMING290414–2421

UPI-C42/UPI-L42WAVEFORMS (Continued)COMBINATION PROGRAM/VERIFY MODE290414–25NOTES:1. A0must be held low (0V) during program/verify modes.2. For VIH,VI

UPI-C42/UPI-L42WAVEFORMS (Continued)DMA290414–27PORT 2290414–28PORT TIMING DURING EXTERNAL ACCESS (EA)290414–29On the Rising Edge of SYNC and EA is En

UPI-C42/UPI-L42Table 4. UPI Instruction SetMnemonic Description Bytes CyclesACCUMULATORADD A, Rr Add register to A 1 1ADD A,@Rr Add data memory 1 1to

UPI-C42/UPI-L42Table 4. UPI Instruction Set (Continued)Mnemonic Description Bytes CyclesCONTROL (Continued)*SUSPEND Invoke Suspend Power- 1 2down mode

UPI-C42/UPI-L42Table 1. Pin Description (Continued)DIP PLCC QFPSymbol Pin Pin Pin Type Name and FunctionNo. No. No.P20–P2721–24 24–27 39–42 I/O PORT 2

UPI-C42/UPI-L42UPI-C42/L42 PRODUCT SELECTION GUIDEUPI-C42: Low power CHMOS version of the UPI-42.Device Package ROM OTP Comments80C42 N, P S 4K ROM De

UPI-C42/UPI-L42UPI-42 COMPATIBLE FEATURES1. Two Data Bus Buffers, one for input and one foroutput. This allows a much cleaner Master/Slaveprotocol.290

UPI-C42/UPI-L42If ‘‘EN DMA’’ has been executed, P27becomesthe DACK(DMA ACKnowledge) pin. This pin actsas a chip select input for the Data Bus Bufferre

UPI-C42/UPI-L42thereby providing additional user programmablememory space. This feature is enabled by theA20EN instruction and remains enabled until t

UPI-C42/UPI-L42Table 2 covers all suspend mode pin states. In addi-tion to the suspend power down mode, the UPI-C42will also support the NMOS power do

UPI-C42/UPI-L42This circuitry gives the host direct control of port 2bit 1 (P2.1) without intervention by the internal CPU.When this opcode is execute