Intel 21555 User Manual

21555 Non-Transparent PCI-to-PCI BridgeUser Manual July 2001Order Number: 278321–002

100 21555 Non-Transparent PCI-to-PCI Bridge User Manual ArbitrationThe 21555’s internal arbiter may be programmed to park the secondary PCI bus eithe

21555 Non-Transparent PCI-to-PCI Bridge User Manual 101Interrupt and Scratchpad Registers 11This chapter presents the theory of operation informatio

102 21555 Non-Transparent PCI-to-PCI Bridge User Manual Interrupt and Scratchpad Registers— Cleared by writing a 1 to the corresponding status bit in

21555 Non-Transparent PCI-to-PCI Bridge User Manual 103Interrupt and Scratchpad Registers11.3 Doorbell InterruptsA 16-bit software controlled interr

21555 Non-Transparent PCI-to-PCI Bridge User Manual 105Error Handling 12This chapter presents the theory of operation information about the 21555 Er

106 21555 Non-Transparent PCI-to-PCI Bridge User Manual Error Handling12.1.2 Secondary PCI Bus Error SignalsTable 28 describes the secondary PCI bus

21555 Non-Transparent PCI-to-PCI Bridge User Manual 107Error Handling12.2 Parity ErrorsThe 21555 checks, forwards, and generates parity on both the

108 21555 Non-Transparent PCI-to-PCI Bridge User Manual Error HandlingData Parity Error on Primary BusDownstream Delayed Write0 | —• Queues and forwa

21555 Non-Transparent PCI-to-PCI Bridge User Manual 109Error HandlingData Parity Error on Secondary BusDownstream Posted Write— | 0 Transaction comp

21555 Non-Transparent PCI-to-PCI Bridge User Manual 11Preface 1A brief description of the contents of this manual follows. Chapter 1, “Preface” Prov

110 21555 Non-Transparent PCI-to-PCI Bridge User Manual Error Handling12.3 System Error (SERR#) ReportingThe 21555 has two system error pins. Signal

21555 Non-Transparent PCI-to-PCI Bridge User Manual 111JTAG Test Port 13This chapter presents the theory of operation information about the 21555 J

112 21555 Non-Transparent PCI-to-PCI Bridge User Manual JTAG Test Port13.2 Test Access Port ControllerThe test access port controller is a finite-sta

21555 Non-Transparent PCI-to-PCI Bridge User Manual 113I2O Support 14This chapter presents the theory of operation information about the 21555 I20 s

114 21555 Non-Transparent PCI-to-PCI Bridge User Manual I2O SupportThe 21555 implements the following hardware for the Inbound Queue:• Table 85, “I2O

21555 Non-Transparent PCI-to-PCI Bridge User Manual 115I2O Supportprocessor removes the message from the Inbound Post_List, it must write bit 31 of

116 21555 Non-Transparent PCI-to-PCI Bridge User Manual I2O Supportand asserts p_inta_l to indicate to the host processor that one or more MFAs exist

21555 Non-Transparent PCI-to-PCI Bridge User Manual 117I2O Support• All MFA counters maintained by the 21555 may be individually loaded with any dat

21555 Non-Transparent PCI-to-PCI Bridge User Manual 119VPD Support 15This chapter presents the theory of operation information about the 21555 Vital

12 21555 Non-Transparent PCI-to-PCI Bridge User Manual Preface1.1 Cautions and NotesCaution: Cautions provide information to prevent damage to equipm

120 21555 Non-Transparent PCI-to-PCI Bridge User Manual VPD Support15.2 Writing VPD InformationA write can occur only to the last 2 Kb (256 bytes) of

21555 Non-Transparent PCI-to-PCI Bridge User Manual 121List of RegistersList of Registers 16This chapter contains reference information about all of

122 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers• “Via Setup” refers to the base address setup register corresponding to tha

21555 Non-Transparent PCI-to-PCI Bridge User Manual 123List of Registers2F:2E6F:6ESubsystem ID Register, page 1540000 Y Secondary Y33:30 (P)73:70 (S

124 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers7D (P)3D (S)Primary and Secondary Interrupt Pin Registers, page 15500 — NY7E

21555 Non-Transparent PCI-to-PCI Bridge User Manual 125List of RegistersC7:C4Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup Registers

126 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers16.3 Control and Status RegistersThe control and status registers are memory

21555 Non-Transparent PCI-to-PCI Bridge User Manual 127List of Registers01B:018Downstream I/O Data and Upstream I/O Data Registers, page 145Downstre

128 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers057:054I2O Outbound Post_List Head Pointer, page 167I20 Outbound Post Head P

21555 Non-Transparent PCI-to-PCI Bridge User Manual 129List of Registers093:090Upstream Page Boundary IRQ Mask 0 Register, page 172Upstream Page Bou

21555 Non-Transparent PCI-to-PCI Bridge User Manual 13Preface1.4 Signal Nomenclature21555 device signal names are printed in lowercase type. Prefixe

130 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers16.4 Address Decoding16.4.1 Primary and Secondary Address This section cover

21555 Non-Transparent PCI-to-PCI Bridge User Manual 131List of Registers3 Prefetchable RIndicates whether the region is prefetchable. Accesses to th

132 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers3 Prefetchable RIndicates if this space is prefetchable.• When a 0, do not u

21555 Non-Transparent PCI-to-PCI Bridge User Manual 133List of RegistersTable 37. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR Bit N

134 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 38. Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BARBit Name

21555 Non-Transparent PCI-to-PCI Bridge User Manual 135List of RegistersTable 39. Upper 32 Bits Downstream Memory 3 Bar• Primary byte offset: 27:24

136 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 41. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Translat

21555 Non-Transparent PCI-to-PCI Bridge User Manual 137List of RegistersTable 42. Downstream Memory 0, 2, 3, and Upstream Memory 1 Translated Base

138 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 43. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup Reg

21555 Non-Transparent PCI-to-PCI Bridge User Manual 139List of RegistersTable 44. Downstream Memory 0, 2, 3, and Upstream Memory 1 Setup RegistersT

14 21555 Non-Transparent PCI-to-PCI Bridge User Manual Preface1.5 Register AbbreviationsWhen a register is associated with the primary interface, its

140 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers16.4.2 Configuration Transaction Generation RegistersAll of these registers

21555 Non-Transparent PCI-to-PCI Bridge User Manual 141List of Registers.Table 46. Downstream and Upstream Configuration Address RegistersThis sect

142 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 47. Downstream Configuration Data and Upstream Configuration Data Reg

21555 Non-Transparent PCI-to-PCI Bridge User Manual 143List of Registers7:1 Reserved R Read only as 0.8Upstream Configuration Own BitR0TS (S)R(P)Ind

144 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers9Upstream Configuration ControlR/WEnables the 21555 to perform upstream indi

21555 Non-Transparent PCI-to-PCI Bridge User Manual 145List of RegistersTable 51. Downstream I/O Data and Upstream I/O Data RegistersThe Downstream

146 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 53. I/O CSR• Byte Offset: 027:026hBit Name R/W Description0Downstream

21555 Non-Transparent PCI-to-PCI Bridge User Manual 147List of Registers16.5 PCI Registers This section covers pages 16-147 through 16-165 and Tab

148 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 57. Primary Interface Configuration Space Address MapByte 3 Byte 2

21555 Non-Transparent PCI-to-PCI Bridge User Manual 149List of Registers16.5.2 Primary and Secondary Command RegistersThe register types in this sec

21555 Non-Transparent PCI-to-PCI Bridge User Manual 15Introduction 2The Intel® 21555 is a PCI peripheral device that performs PCI bridging functions

150 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers7Wait Cycle ControlRReads as zero to indicate the 21555 does not perform add

21555 Non-Transparent PCI-to-PCI Bridge User Manual 151List of Registers8Data Parity DetectedR/W1TCThis bit is set to a 1 when all of the following

152 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 64. Primary and Secondary Class Code RegistersThese registers may be

21555 Non-Transparent PCI-to-PCI Bridge User Manual 153List of RegistersTable 66. Primary Latency and Secondary Master Latency Timer RegistersBit N

154 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersPrTable 69. Subsystem Vendor ID Register• Primary byte offset: 2D:2Ch and 6

21555 Non-Transparent PCI-to-PCI Bridge User Manual 155List of RegistersTable 73. Primary and Secondary Interrupt Pin RegistersBit Name R/W Descrip

156 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers16.5.3 Device-Specific Control and Status RegistersThis section contains inf

21555 Non-Transparent PCI-to-PCI Bridge User Manual 157List of Registers3Secondary Master TimeoutR/WSets the maximum number of PCI clock cycles that

158 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers8Upstream DAC Prefetch DisableR/WControls prefetching for upstream dual addr

21555 Non-Transparent PCI-to-PCI Bridge User Manual 159List of Registers12LUT Page Size Extension BitR/WAllows selection of larger page sizes when p

16 21555 Non-Transparent PCI-to-PCI Bridge User Manual IntroductionA primary goal of the PPB architecture is that PPB are transparent to devices and

160 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 78. Chip Control 1 Register (Sheet 1 of 3)This register may be preloa

21555 Non-Transparent PCI-to-PCI Bridge User Manual 161List of Registers7:6Subtractive Decode EnableR/WControls subtractive decoding for downstream

162 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers12 I20_ENA R/WEnables the I20 message unit.• When 0, the I20 message unit i

21555 Non-Transparent PCI-to-PCI Bridge User Manual 163List of Registers3Downstream Posted Write Data DiscardedR/W1TCThis bit is set to a 1 and p_se

164 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 80. Generic Own Bits RegisterThe 21555 implements two generic own bit

21555 Non-Transparent PCI-to-PCI Bridge User Manual 165List of Registers16.6 I2O RegistersThis section contains a description of the I2O registers.

166 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 84. I2O Inbound Post_List Interrupt MaskByte Offset: 3F:3ChBit Name R

21555 Non-Transparent PCI-to-PCI Bridge User Manual 167List of Registers Table 87. I2O Inbound Free_List Head PointerByte Offsets: 04B:048hBit Name

168 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 91. I2O Inbound Post_List CounterByte Offsets: 05B:058hBit Name R/W D

21555 Non-Transparent PCI-to-PCI Bridge User Manual 169List of RegistersTable 93. I2O Outbound Post_List CounterByte Offsets: 063:060hBit Name R/W D

21555 Non-Transparent PCI-to-PCI Bridge User Manual 17IntroductionTable 3 shows compares a 21555 and to a transparent PPB.Table 3. 21555 and PPB F

170 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers16.7 Interrupt RegistersThis section contains information about interrupt re

21555 Non-Transparent PCI-to-PCI Bridge User Manual 171List of RegistersTable 97. Chip Clear IRQ Mask RegisterByte Offsets: 087:086hBit Name R/W De

172 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 99. Upstream Page Boundary IRQ 1 RegisterByte Offset: 08F:08ChBit Nam

21555 Non-Transparent PCI-to-PCI Bridge User Manual 173List of Registers Table 102. Primary Clear IRQ and Secondary Clear IRQ RegistersThese registe

174 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers16.8 Scratchpad RegistersSee Chapter 11 for theory of operation information.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 175List of Registers16.9 PROM RegistersThis section describes the six PROM registers. See Chapte

176 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 108. Primary Expansion ROM Setup RegisterThis register may be preload

21555 Non-Transparent PCI-to-PCI Bridge User Manual 177List of Registers Table 109. ROM Setup RegisterByte Offsets: 0C9:0C8hBit Name R/W Description

178 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 111. ROM Address RegisterByte Offsets: 0CE:0CChBit Name R/W Descripti

21555 Non-Transparent PCI-to-PCI Bridge User Manual 179List of Registers16.10 SROM RegistersThis sections describes the SROM registers. See Chapter

18 21555 Non-Transparent PCI-to-PCI Bridge User Manual Introduction2.2 Architectural OverviewThis section describes the buffers, registers, and contr

180 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers3s_clk_o EnableRIndicates whether s_clk_o is enabled, determined by sampling

21555 Non-Transparent PCI-to-PCI Bridge User Manual 181List of Registers09h Subsystem ID [7:0]0Ah Subsystem ID [15:8]0Bh Primary Minimum Grant0Ch Pr

182 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers2Bh Upstream I/O or Memory 0 Setup [31:24]2Ch Upstream Memory 1 Setup [7:0].

21555 Non-Transparent PCI-to-PCI Bridge User Manual 183List of Registers16.11 Arbiter Control This chapter describes the arbitration control registe

184 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 116. Primary SERR# Disable RegisterThis register may be preloaded by s

21555 Non-Transparent PCI-to-PCI Bridge User Manual 185List of Registers16.13 Init RegistersThis section describes the Power management, Reset, and

186 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers.Table 119. Power Management Capabilities RegisterBits [14:9,5,2:0] are load

21555 Non-Transparent PCI-to-PCI Bridge User Manual 187List of RegistersTable 120. Power Management Control and Status RegisterBits [14:13] are load

188 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersTable 122. Power Management Data Register• Primary byte offset: E3h• Seconda

21555 Non-Transparent PCI-to-PCI Bridge User Manual 189List of RegistersTable 124. CompactPCI Hot-Swap Capability Identifier and Next Pointer Regist

21555 Non-Transparent PCI-to-PCI Bridge User Manual 19IntroductionFigure 2 shows the 21555 microarchitecture. Figure 2. 21555 MicroarchitectureA741

190 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers16.14 JTAG RegistersThis chapter presents the theory of operation informatio

21555 Non-Transparent PCI-to-PCI Bridge User Manual 191List of RegistersTable 129. Boundary Scan OrderTBD table lists the boundary-scan register ord

192 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of RegistersThe group disable number column in TBD shows which group disable bit control

21555 Non-Transparent PCI-to-PCI Bridge User Manual 193List of RegistersTable 131. Vital Product Data (VPD) Address Register• Primary byte offset: E

21555 Non-Transparent PCI-to-PCI Bridge User Manual 205Acronyms A• 1D – One-dimensional • 2D – Two-dimensional • AGP – Accelerated Graphics Port • A

206 21555 Non-Transparent PCI-to-PCI Bridge User Manual Acronyms• MFAs – Message Frame Addresses • MPEG – Moving Pictures Experts Group • MV – Motion

21555 Non-Transparent PCI-to-PCI Bridge User Manual 197Index3-V 155-V 15Primary lockout biton the PROM_AD 82AAdd-in card vendors 15address 33Address

198 21555 Non-Transparent PCI-to-PCI Bridge User Manual Primary Lockout bitaction before clearing the 130power management 71with serial Preload 69with

2 21555 Non-Transparent PCI-to-PCI Bridge User Manual Information in this document is provided in connection with Intel® products. No license, expres

20 21555 Non-Transparent PCI-to-PCI Bridge User Manual Introduction2.3 Special Applications2.3.1 Primary Bus VGA SupportThe 21555 provides hardware s

21555 Non-Transparent PCI-to-PCI Bridge User Manual 21Introduction• Setting a translated base address for a downstream range to fall within an addre

21555 Non-Transparent PCI-to-PCI Bridge User Manual 23Signal Descriptions 3This chapter presents the theory of operation information about the PCI s

24 21555 Non-Transparent PCI-to-PCI Bridge User Manual Signal Descriptions3.1 Primary PCI Bus Interface SignalsTable 6 describes the primary PCI bus

21555 Non-Transparent PCI-to-PCI Bridge User Manual 25Signal Descriptionsp_par TSPrimary PCI interface parity. Signal p_par carries the even parity

26 21555 Non-Transparent PCI-to-PCI Bridge User Manual Signal Descriptions3.2 Primary PCI Bus Interface 64-Bit Extension Signals Table 7 describes th

21555 Non-Transparent PCI-to-PCI Bridge User Manual 27Signal Descriptionsp_par64 TSPrimary PCI interface upper 32 bits parity. The 21555 does not bu

28 21555 Non-Transparent PCI-to-PCI Bridge User Manual Signal Descriptions3.3 Secondary PCI Bus Interface SignalsTable 8 describes the secondary PCI

21555 Non-Transparent PCI-to-PCI Bridge User Manual 29Signal Descriptionss_par TSSecondary PCI interface parity. Signal s_par carries the even parit

21555 Non-Transparent PCI-to-PCI Bridge User Manual 3ContentsContents1 Preface ...

30 21555 Non-Transparent PCI-to-PCI Bridge User Manual Signal Descriptions3.4 Secondary PCI Bus Interface 64-Bit Extension Signals Table 9 describes

21555 Non-Transparent PCI-to-PCI Bridge User Manual 31Signal Descriptions3.5 Miscellaneous SignalsTable 10 describes the miscellaneous signals. The

21555 Non-Transparent PCI-to-PCI Bridge User Manual 33Address Decoding 4This chapter presents the theory of operation information about address mapp

34 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address Decoding4.1 CSR Address DecodingThe 21555 implements a set of CSRs that are mapped in

21555 Non-Transparent PCI-to-PCI Bridge User Manual 35Address Decoding4.3.1 Using the BAR Setup RegistersAll downstream and upstream BARs have progr

36 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address Decoding4.3.2 Direct Address TranslationWith the exception of secondary bus transactio

21555 Non-Transparent PCI-to-PCI Bridge User Manual 37Address DecodingThis new base address, also called the translated base address, references a n

38 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address DecodingThe Upstream Memory 2 address range consists of a fixed number (64) of pages.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 39Address DecodingFigure 7 shows how a translated address is built using the lookup table, assum

4 21555 Non-Transparent PCI-to-PCI Bridge User Manual Contents5.2 Posted Write Transactions...

40 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address DecodingNote: The indirect access mechanism must be used only by one interface at a ti

21555 Non-Transparent PCI-to-PCI Bridge User Manual 41Address DecodingNote: The lookup table is not cleared by reset. The lookup table must be initi

42 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address Decodingthe Downstream memory 3 address range must be set to a non-zero value when the

21555 Non-Transparent PCI-to-PCI Bridge User Manual 43Address Decodingtransaction. One pair is used for downstream I/O transactions and one pair is

44 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address Decoding4.4.2 Subtractive Decoding of I/O TransactionsThe 21555 can be enabled to subt

21555 Non-Transparent PCI-to-PCI Bridge User Manual 45Address DecodingAccesses to the 21555 configuration space are not ordered with respect to tran

46 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address DecodingThe 21555 provides a semaphore method that may be used to guarantee atomicity

21555 Non-Transparent PCI-to-PCI Bridge User Manual 47Address Decoding4.6 21555 Bar SummaryTable 12 shows a summary of the 21555 BARs.Table 12. Bar

21555 Non-Transparent PCI-to-PCI Bridge User Manual 49PCI Bus Transactions 5This chapter presents the theory of operation information about PCI tran

21555 Non-Transparent PCI-to-PCI Bridge User Manual 5Contents9.2 SROMSROM Preload Operation...

50 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus Transactions5.2 Posted Write TransactionsThis section discusses the following Posted W

21555 Non-Transparent PCI-to-PCI Bridge User Manual 51PCI Bus Transactions5.2.1 Memory Write TransactionsAs a target, the 21555 disconnects memory w

52 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus TransactionsWhen any of these conditions is not met, the 21555 uses the memory write c

21555 Non-Transparent PCI-to-PCI Bridge User Manual 53PCI Bus Transactions5.2.4.3 Write-ThroughWhen the 21555 is able to obtain access to the target

54 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus Transactions5.3 Delayed Write TransactionsThe 21555 uses delayed transactions when for

21555 Non-Transparent PCI-to-PCI Bridge User Manual 55PCI Bus TransactionsWhen the initiator repeats the transaction using the same address, bus com

56 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus TransactionsThe 21555 requests the target bus and initiates the delayed read transacti

21555 Non-Transparent PCI-to-PCI Bridge User Manual 57PCI Bus Transactions5.4.2 Prefetchable ReadsThe following transactions are considered by the 2

58 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus TransactionsWhen using the Quadword boundary, REQ64# asserts every time the transactio

21555 Non-Transparent PCI-to-PCI Bridge User Manual 59PCI Bus Transactions5.4.4.3 Read Queue Full Threshold TuningThe 21555 implements read queue ma

6 21555 Non-Transparent PCI-to-PCI Bridge User Manual Contents16.7 Interrupt Registers...

60 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus Transactions5.6 Target TerminationsThis section describes the following target retries

21555 Non-Transparent PCI-to-PCI Bridge User Manual 61PCI Bus Transactions5.6.2 Transaction Termination Errors on the Target BusWhen the 21555 detec

62 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus Transactions• A target retry in response to a posted write is allowed, but only due to

21555 Non-Transparent PCI-to-PCI Bridge User Manual 63PCI Bus TransactionsNote: Performance may be affected if the Delayed Transaction Order Control

21555 Non-Transparent PCI-to-PCI Bridge User Manual 65Initialization Requirements 6This chapter presents the theory of operation information about t

66 21555 Non-Transparent PCI-to-PCI Bridge User Manual Initialization Requirements6.2 Reset BehaviorThe 21555 implements a primary reset input, p_rst

21555 Non-Transparent PCI-to-PCI Bridge User Manual 67Initialization RequirementsThe secondary reset output, s_rst_l, is asserted and remains assert

68 21555 Non-Transparent PCI-to-PCI Bridge User Manual Initialization Requirements6.2.1 Central Function During ResetThe 21555 is selected to be the

21555 Non-Transparent PCI-to-PCI Bridge User Manual 69Initialization Requirements6.3.1 With SROM, Local, and Host ProcessorsThe following is the 215

21555 Non-Transparent PCI-to-PCI Bridge User Manual 7Contents7 Primary PCI Bus Interface 64-Bit Extension Signals...

70 21555 Non-Transparent PCI-to-PCI Bridge User Manual Initialization RequirementsThe remainder of the 21555 configuration proceeds as described in S

21555 Non-Transparent PCI-to-PCI Bridge User Manual 71Initialization Requirements6.4.1 Transitions Between Power Management StatesThe 21555 is put i

72 21555 Non-Transparent PCI-to-PCI Bridge User Manual Initialization Requirements6.4.3 Power Management Data RegisterThe PCI Power Management specif

21555 Non-Transparent PCI-to-PCI Bridge User Manual 73Initialization RequirementsA CompactPCI hot-swap card also implements an indicator LED. When t

74 21555 Non-Transparent PCI-to-PCI Bridge User Manual Initialization RequirementsThe 21555 enters the Signal Insertion state from the Serial Preload

21555 Non-Transparent PCI-to-PCI Bridge User Manual 75Initialization RequirementsWhen the INS_STAT bit is cleared, the card is ready for normal oper

76 21555 Non-Transparent PCI-to-PCI Bridge User Manual Initialization RequirementsHowever, when the 21555 samples l_stat high once the INS_STAT bit i

21555 Non-Transparent PCI-to-PCI Bridge User Manual 77Clocking 7The 21555 supports two clock inputs, p_clk and s_clk. The signal p_clk corresponds t

78 21555 Non-Transparent PCI-to-PCI Bridge User Manual Clocking7.2 21555 Secondary Clock OutputsWhen the secondary clock is not supplied independentl

21555 Non-Transparent PCI-to-PCI Bridge User Manual 79Clocking7.3 66 MHz SupportThe 21555 supports 66 MHz operation. It has two pins, p_m66ena and s

8 21555 Non-Transparent PCI-to-PCI Bridge User Manual Contents57 Primary Interface Configuration Space Address Map ...

21555 Non-Transparent PCI-to-PCI Bridge User Manual 81Parallel ROM Interface 8This chapter presents the theory of operation information about the 21

82 21555 Non-Transparent PCI-to-PCI Bridge User Manual Parallel ROM InterfaceTable 21. PROM Interface Signals (Sheet 1 of 2)Signal NameType Descrip

21555 Non-Transparent PCI-to-PCI Bridge User Manual 83Parallel ROM Interfacepr_ale_l O PROM address latch enable/chip select decoder enable. The si

84 21555 Non-Transparent PCI-to-PCI Bridge User Manual Parallel ROM Interface8.2 Parallel and Serial ROM ConnectionFigure 14 shows how a parallel and

21555 Non-Transparent PCI-to-PCI Bridge User Manual 85Parallel ROM InterfaceWhen a byte read of the PROM is performed, the 21555 follows this sequen

86 21555 Non-Transparent PCI-to-PCI Bridge User Manual Parallel ROM Interface8.4 PROM Write by CSR AccessByte writes of the PROM can be performed by

21555 Non-Transparent PCI-to-PCI Bridge User Manual 87Parallel ROM Interface. 8.5 PROM Dword ReadA Dword read is performed on the PROM interface whe

88 21555 Non-Transparent PCI-to-PCI Bridge User Manual Parallel ROM Interface8.6 Access Time and Strobe ControlThe 21555 controls both the access tim

21555 Non-Transparent PCI-to-PCI Bridge User Manual 89Parallel ROM Interface8.7 Attaching Additional Devices to the ROM InterfaceThe 21555 allows ad

21555 Non-Transparent PCI-to-PCI Bridge User Manual 9Contents107 Primary Expansion ROM BAR...

90 21555 Non-Transparent PCI-to-PCI Bridge User Manual Parallel ROM Interface. Figure 18. Attaching Multiple Devices on the ROM InterfaceA7473-01Othe

21555 Non-Transparent PCI-to-PCI Bridge User Manual 91Serial ROM Interface 9This chapter presents the theory of operation information about the 2155

92 21555 Non-Transparent PCI-to-PCI Bridge User Manual Serial ROM Interface9.3 SROM Configuration Data Preload FormatSome fields of the 21555 configu

21555 Non-Transparent PCI-to-PCI Bridge User Manual 93Serial ROM InterfacePrior to a SROM write or write all transaction, the 8-bit write data must

94 21555 Non-Transparent PCI-to-PCI Bridge User Manual Serial ROM InterfaceNote: When a SROM access using the CSR mechanism is attempted when the SRO

21555 Non-Transparent PCI-to-PCI Bridge User Manual 95Serial ROM InterfaceFigure 22. SROM Erase Timing DiagramFigure 23. SROM Erase All OperationFig

21555 Non-Transparent PCI-to-PCI Bridge User Manual 97Arbitration 10This chapter describes the arbitration signals. It also describes how the 21555

98 21555 Non-Transparent PCI-to-PCI Bridge User Manual Arbitration10.3 Primary PCI Bus ArbitrationThe 21555 implements primary PCI bus request and gr

21555 Non-Transparent PCI-to-PCI Bridge User Manual 99Arbitration.Each bus master, including the 21555, may be configured to be in either the low pr