Intel S3420GP User Manual Page 107
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IntelP®P Server Board S3420GP TPS Design and Environmental Specifications
9.4.11 Residual Voltage Immunity in Standby Mode
The power supply is immune to any residual voltage placed on its outputs (typically, a leakage
voltage through the system from standby output) up to 500 mV. There is no additional heat
generated nor stressing of any internal components with this voltage applied to any individual
output and all outputs simultaneously. It also does not trip the power supply protection circuits
during turn on.
The residual voltage at the power supply outputs for a no-load condition does not exceed 100
mV when AC voltage is applied and the PSON# signal is de-asserted.
9.4.12 Protection Circuits
Protection circuits inside the power supply should cause only the power supply’s main outputs
to shut down. If the power supply latches off due to a protection circuit tripping, an AC cycle
OFF for 15 seconds and a PSON
#
cycle HIGH for 1 second should reset the power supply.
9.4.12.1 Over-current Protection (OCP)
The power supply has current limits to prevent the +3.3 V, +5 V, and +12 V outputs from
exceeding the values shown in the following table. If the current limits are exceeded, the power
supply shuts down and latches off. The latch is cleared by toggling the PSON
#
signal or using
an AC power interruption. The power supply is not damaged from repeated power cycling in this
condition. -12 V and 5 VSB are protected under over-current or shorted conditions so no
damage can occur to the power supply. Auto-recovery feature is a requirement on 5 VSB rail.
Table 64. Over-Current Protection (OCP)
VOLTAGE OVER CURRENT LIMIT
Min Max
+3.3V 15A 21A
+5V 20A 27A
+12V 30A 40A
-12V 0.625A 2A
5VSB N/A 4A
9.4.12.2 Over-Voltage Protection (OVP)
The power supply over-voltage protection is locally sensed. The power supply shuts down and
latches off after an over-voltage condition occurs. You can clear this latch by toggling the
PSON
#
signal or using an AC power interruption. The following table contains the over-voltage
limits. The values are measured at the output of the power supply’s connectors. The voltage
never exceeds the maximum levels when measured at the power pins of the power supply
connector during any single point of fail. The voltage never trips any lower than the minimum
levels when measured at the power pins of the power supply connector.
Exception: +5 VSB rail should be able to recover after an over-voltage condition occurs.
Table 65. Over-voltage Protection (OVP) Limits
Output Voltage Minimum (V) Maximum (V)
+3.3 V 3.9 4.5
Revision 1.0
Intel order number E65697-003
93
- Intel Server Board S3420 1
- Revision History 2
- Disclaimers 3
- Table of Contents 4
- List of Figures 8
- List of Tables 10
- 1. Introduction 14
- 2. Overview 15
- 2.2 Server Board Layout 17
- AF003290 18
- 2.2.2 Intel 20
- Server Board Rear I/O Layout 26
- 3 nct. Fu ional Architecture 27
- Intel Xeon 28
- Processor 28
- 3.2 Memory Subsystem 29
- 3.2.2 Post Error Codes 30
- 3 Publishing System Memory 31
- 3.2.4 Support for Mi 32
- 3.3 Intel 35
- 3420 Chipset PCH 35
- 3.4 I/O Sub 35
- -system 35
- 3.4.2 Serial ATA Support 36
- 3.4.3 USB 2.0 Support 36
- 3.5 Optional 37
- SAS Entry RAI 37
- Intel D Module AXX4SASMOD 37
- Integrated BMC Block Diagram 39
- 3.6.3 Serial Ports 40
- Floppy Disk Controller 40
- Keyboard and Mouse Support 40
- Video Support 41
- 3.8 ller (NIC) 42
- Network Interface Contro 42
- Direct Cache Access (DCA) 43
- 4. Platform Management 44
- 4.1.2 Non-IPMI Features 45
- Revision 1.0 46
- 4.2.3 Media Redirection 47
- 4.2.5 Local Directory Aut 48
- 4.2.6 Embedde 48
- 5. BIOS User Interface 49
- Server Pla U 52
- 56
- 5.4 Loading BIOS Defaults 77
- 6.2 Power Connectors 79
- 6.3.1 Intel 80
- RMM3) Connector 80
- 6.4.1 Power Button 82
- 6.5 I/O Connectors 85
- 6.5.3 SATA 86
- 6.5.4 SAS Connectors 86
- 6.5.6 USB Connector 87
- One PCI X32 connector (J1B1) 92
- 6.7 Fan Headers 93
- 7. Jumper Blocks 94
- 7.1.1 Clearing the CMOS 95
- 7.1.2 Clearing the Password 95
- 7.3 ME Force Update Jumper 96
- 7.4 BIOS Recovery Jumper 97
- 8. Intel 98
- Light Guided Diagnostics 98
- 9.1 Intel 100
- Revision 1.0 101
- 9.4.1 Grounding 103
- 9.4.2 Standby Outputs 103
- 9.4.3 Remote Sense 103
- 9.4.4 Voltage Regulation 103
- 9.4.5 Dynamic Loading 103
- 9.4.6 Capacitive Loading 104
- 9.4.7 Closed-loop Stability 104
- 9.4.8 Common Mode Noise 104
- 9.4.9 Ripple / Noise 104
- 9.4.10 Timing Requirements 104
- 9.4.12 Protection Circuits 107
- Revision 1.0 108
- IntelP®P Serv 115
- Appendix D: POST Code Errors 127
- Pause 130
- POST Error Beep Codes 131
- Glossary 133
- Reference Documents 136
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