Intel Core 2 Quad Q6700 Datasheet download pdf (Page 16)

Electrical Specifications

16 Datasheet

2.4 Reserved, Unused, and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to V

, V

, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Chapter 4 for a land listing of the

processor and the location of all RESERVED lands.

In a system level design, on-die termination has been included by the processor to

allow signals to be terminated within the processor silicon. Most unused GTL+ inputs

should be left as no connects as GTL+ termination is provided on the processor silicon.

However, see Table 7 for details on GTL+ signals that do not include on-die termination.

Unused active high inputs, should be connected through a resistor to ground (V

Unused outputs can be left unconnected, however this may interfere with some TAP

functions, complicate debug probing, and prevent boundary scan testing. A resistor

must be used when tying bidirectional signals to power or ground. When tying any

signal to power or ground, a resistor will also allow for system testability. Resistor

values should be within ± 20% of the impedance of the motherboard trace for front

side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the

same value as the on-die termination resistors (RTT). For details see Table 14.

TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs

must be terminated on the motherboard. Unused outputs may be terminated on the

motherboard or left unconnected. Note that leaving unused outputs unterminated may

interfere with some TAP functions, complicate debug probing, and prevent boundary

scan testing.

All TESTHI[13,11:10,7:0] lands should be individually connected to V

via a pull-up

resistor which matches the nominal trace impedance.

The TESTHI signals may use individual pull-up resistors or be grouped together as

detailed below. A matched resistor must be used for each group:

•TESTHI[1:0]

•TESTHI[7:2]

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

However, use of boundary scan test will not be functional if these lands are connected

together. For optimum noise margin, all pull-up resistor values used for

TESTHI[13,11:10,7:0] lands should have a resistance value within ±20% of the

impedance of the board transmission line traces. For example, if the nominal trace

impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.

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Intel Core 2 Quad Q6700 Datasheet Page 16