Intel BK80524P533128 Datasheet download pdf (Page 125)

Datasheet 125

Intel

Celeron

Processor up to 1.10 GHz

SMI# I

The SMI# (System Management Interrupt) signal is asserted asynchronously by

system logic. On accepting a System Management Interrupt, processors save the

current state and enter System Management Mode (SMM). An SMI Acknowledge

transaction is issued, and the processor begins program execution from the SMM

handler.

STPCLK# I

The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low

power Stop-Grant state. The processor issues a Stop-Grant Acknowledge

transaction, and stops providing internal clock signals to all processor core units

except the bus and APIC units. The processor continues to snoop bus transactions

and may latch interrupts while in Stop-Grant state. When STPCLK# is deasserted,

the processor restarts its internal clock to all units, resumes execution, and services

any pending interrupt. The assertion of STPCLK# has no effect on the bus clock;

STPCLK# is an asynchronous input.

TCK I

The TCK (Test Clock) signal provides the clock input for the Intel Celeron processor

Test Access Port.

TDI I

The TDI (Test Data In) signal transfers serial test data into the processor. TDI

provides the serial input needed for JTAG specification support.

TDO O

The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TESTHI

(S.E.P.P. only)

I Refer to Section 2.6 for implementation details.

THERMDN O Thermal Diode p-n junction. Used to calculate core temperature. See Section 4.1.

THERMDP I Thermal Diode p-n junction. Used to calculate core temperature. See Section 4.1.

THERMTRIP# O

The processor protects itself from catastrophic overheating by use of an internal

thermal sensor. This sensor is set well above the normal operating temperature to

ensure that there are no false trips. The processor will stop all execution when the

junction temperature exceeds approximately 135 °C. This is signaled to the system

by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains latched,

and the processor stopped, until RESET# goes active. There is no hysteresis built

into the thermal sensor itself; as long as the die temperature drops below the trip

level, a RESET# pulse will reset the processor and execution will continue. If the

temperature has not dropped below the trip level, the processor will reassert

THERMTRIP# and remain stopped. The system designer should not act upon

THERMTRIP# until after the RESET# input is deasserted. Until this time, the

THERMTRIP# is indeterminate.

TMS I

The TMS (Test Mode Select) signal is a JTAG specification support signal used by

debug tools.

TRDY# I

The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready

to receive a write or implicit writeback data transfer. TRDY# must connect the

appropriate pins of all system bus agents.

TRST# I

The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. Intel

Celeron processors require this signal to be driven low during power on Reset. A

680 ohm resistor is the suggested value for a pull down resistor on TRST#.

1.5

(PGA packages

only)

The V

CMOS

pin provides the CMOS voltage for use by the platform. The 2.5 V

must be provided to the V

2.5

input and 1.5 V must be provided to the VCC

1.5

input.

The processor re-routes the 1.5 V input to the V

CMOS

output via the package. The

supply for V

1.5

must be the same one used to supply VTT

VCC

2.5

(PGA packages

only)

The V

CMOS

pin provides the CMOS voltage for use by the platform. The 2.5 V

must be provided to the V

2.5

input and 1.5 V must be provided to the VCC

1.5

input.

The processor re-routes the 2.5 V input to the V

CMOS

output via the package.

CMOS

(PGA packages

only)

The V

CMOS

pin provides the CMOS voltage for use by the platform. The 2.5 V

must be provided to the V

2.5

input and 1.5 V must be provided to the VCC

1.5

input.

Table 59. Alphabetical Signal Reference (Sheet 6 of 7)

Signal Type Description

1 2 ... 120 121 122 123 124 125 126 127 128

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