Intel Switch 317698-001 User Manual

Intel® 82575 Gigabit Ethernet ControllerDesign Guide V1.00June 2007317698-001

82575 Ethernet Controller Design Guide4• If Maximum Link Width = x2, then the 82575 Ethernet Controller negotiates to either x2 or x1• If Maximum Link

582575 Ethernet Controller Design GuideFigure 1. Lane Reversal supported modes Configuration bits: EEPROM "Lane reversal disable" bit - disa

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782575 Ethernet Controller Design Guide3.0 Ethernet Component Design GuidelinesThese sections provide recommendations for selecting components and con

82575 Ethernet Controller Design Guide8consistent from sample to sample and that measurements meet the published specifications.3. Perform physical la

982575 Ethernet Controller Design Guide3.2.1 LAN Disable for 82575 Ethernet Controller Gigabit Ethernet ControllerThe 82575 Ethernet Controller device

82575 Ethernet Controller Design Guide10Table 2. Strapping Options for LAN DisableTable 3. Control Options for LAN Disable3.2.2 Serial EEPROM The 8257

1182575 Ethernet Controller Design Guide• Legacy Wake On LAN (magic packets) is not supported• All the initializations normally loaded from the EEPROM

82575 Ethernet Controller Design Guide12Table 5. 82575 Ethernet Controller EEPROM Memory Layout3.2.3.1 EEUPDATEIntel has an MS-DOS* software utility c

1382575 Ethernet Controller Design Guide2. A particular address range of the IOADDR register defined by the IO Base Address Register (PCIe Control Reg

iiLegal Lines and Disclaime rsINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL

82575 Ethernet Controller Design Guide14Note: Sector erase by SW is not supported. In order to delete a sector, the serial (bit bang) interface should

1582575 Ethernet Controller Design GuideFigure 2. External BMC Connections with NC-SI and SMBThe 82575 Ethernet Controller also supports the DMTF prot

82575 Ethernet Controller Design Guide16Figure 3. Example Switching Voltage Regulator for 1.0 V and 1.8 VDNGGNIHCTIWS_0V1CCV3V3CCV>>noitceleS ro

1782575 Ethernet Controller Design GuideThe 1.8 V rail has a lower current requirement; however, the use of a SVR is still recommended for adequate ma

82575 Ethernet Controller Design Guide18Figure 5. Proper power sequencing for 82575 Ethernet ControllerFigure 6. Power On FlowchartIn addition, the fo

1982575 Ethernet Controller Design Guide• 1.8 V must not exceed 3.3 V.• 1.0 V must not exceed 3.3 V.• 1.0 V must not exceed 1.8 V.The power supplies a

82575 Ethernet Controller Design Guide20logic input to the 82575 Ethernet Controller that denotes auxiliary power is available. If AUX_PWR is asserted

2182575 Ethernet Controller Design GuideFigure 8. PCIe Power Management Flow/State Diagram3.4.4.2 82575 Ethernet Controller Power ManagementIf Disable

82575 Ethernet Controller Design Guide223.5 82575 Ethernet Controller Device Test Capability The 82575 Ethernet Controller Gigabit Ethernet Controller

2382575 Ethernet Controller Design Guide3.6.2 Smartspeed SmartSpeed is an enhancement to auto-negotiation that allows the PHY to react to network cond

iii82575 Ethernet Controller Design GuideContents1.0 Introduction ...

82575 Ethernet Controller Design Guide24The table below summarizes link speed as function of power management state, link speed control, and gigabit s

2582575 Ethernet Controller Design Guide3.6.7 Auto-Negotiation differences between PHY, SerDes and SGMIISGMII protocol includes an auto-negotiation pr

82575 Ethernet Controller Design Guide26is complete, the driver must read the PHY registers to determine the resolved flow control behavior of the lin

2782575 Ethernet Controller Design Guide• The 82575 will put the PHY in power down unless CONNSW.ASCLR_DIS is set. In such a case the host driver is r

82575 Ethernet Controller Design Guide28Note that if the device is configured to provide a 50MHz NC-SI clock (via the NC-SI Output Clock EEPROM bit),

2982575 Ethernet Controller Design GuideNote: To avoid signal contention, all four pins are set as input pins until after EEPROM configuration has bee

82575 Ethernet Controller Design Guide304.0 Frequency Control Device Design ConsiderationsThis section provides information regarding frequency contro

3182575 Ethernet Controller Design Guide4.1.3 Programmable Crystal OscillatorsA programmable oscillator can be configured to operate at many frequenci

82575 Ethernet Controller Design Guide325.0 Crystal Selection ParametersAll crystals used with Intel Ethernet controllers are described as “AT-cut,” w

3382575 Ethernet Controller Design GuideNote: Crystals also carry other specifications for storage temperature, shock resistance, and reflow solder co

82575 Ethernet Controller Design Guideiv5.3 Frequency Tolerance ...

82575 Ethernet Controller Design Guide34An allowance of 3 pF to 7 pF accounts for lumped stray capacitance. The calculated load capacitance is 16 pF w

3582575 Ethernet Controller Design GuideEven with a perfect support circuit, most crystals will oscillate slightly higher or slightly lower than the e

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3782575 Ethernet Controller Design Guide6.0 Oscillator SupportThe 82575 clock input circuit is optimized for use with an external crystal. However, an

82575 Ethernet Controller Design Guide38A low capacitance, high impedance probe (C < 1 pF, R > 500 KΩ) should be used for testing. Probing the p

3982575 Ethernet Controller Design Guide7.0 Ethernet Component Layout GuidelinesThese sections provide recommendations for performing printed circuit

82575 Ethernet Controller Design Guide40Minimizing the amount of space needed for the Ethernet LAN interface is important because other interfaces wil

4182575 Ethernet Controller Design GuideFigure 13. Layout for Integrated MagneticsFigure 14. Layout for Discrete MagneticsTermination resistorsplaced

82575 Ethernet Controller Design Guide427.1.2 Crystals and OscillatorsClock sources should not be placed near I/O ports or board edges. Radiation fro

4382575 Ethernet Controller Design GuideFigure 15. Recommended Crystal Placement and Layout7.1.3 Board Stack Up RecommendationsPrinted circuit boards

v82575 Ethernet Controller Design GuideRevision HistoryDate Revision Description0.25 Jan 2006 Initial publication of preliminary design guide informat

82575 Ethernet Controller Design Guide447.1.4 Differential Pair Trace Routing for 10/100/1000 DesignsTrace routing considerations are important to min

4582575 Ethernet Controller Design Guide7.1.4.1 Signal Termination and CouplingThe four differential pairs of each port are terminated with 49.9 Ω (1%

82575 Ethernet Controller Design Guide467.1.6.1 Signal DetectEach port of the 82575 controller has a Signal Detect pin for connection to optical trans

4782575 Ethernet Controller Design Guide• Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission and susce

82575 Ethernet Controller Design Guide487.1.14 Thermal Design ConsiderationsThe 82575 Gigabit Ethernet Controller contains a thermal sensor that is ac

4982575 Ethernet Controller Design Guidewhere the traces enter or exit the magnetics, the RJ-45 connector, and the Ethernet silicon.6. Use of a low-qu

82575 Ethernet Controller Design Guide508.0 Thermal ManagementPlease see the 82575 Thermal Application Note, available on the Intel Developer site.9.0

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182575 Ethernet Controller Design Guide1.0 IntroductionThe Intel® 82575 Ethernet Controller is a single, compact component that offers two fully-integ

82575 Ethernet Controller Design Guide21.2 Reference DocumentsThis application assumes that the designer is acquainted with high-speed design and boar

382575 Ethernet Controller Design Guide2.0 PCI Express Port Connection to the DevicePCI Express (PCIe*) is a dual simplex point-to-point serial differ