Intel D915PCML Datasheet download pdf (Page 41)

Product Description

1.13.2.3 LAN Wake Capabilities

CAUTION

For LAN wake capabilities, the +5 V standby line for the power supply must be capable of

providing adequate +5 V standby current. Failure to provide adequate standby current when

implementing LAN wake capabilities can damage the power supply.

LAN wake capabilities enable remote wake-up of the computer through a network. The LAN

network adapter monitors network traffic at the Media Independent Interface. Upon detecting a

Magic Packet* frame, the LAN subsystem asserts a wake-up signal that powers up the computer.

Depending on the LAN implementation, the boards support LAN wake capabilities with ACPI in

the following ways:

•

The PCI Express WAKE# signal

•

The PCI Conventional bus PME# signal for PCI 2.2 compliant LAN designs

•

The onboard LAN subsystem

1.13.2.4 Instantly Available PC Technology

CAUTION

For Instantly Available PC technology, the +5 V standby line for the power supply must be

capable of providing adequate +5 V standby current. Failure to provide adequate standby current

when implementing Instantly Available PC technology can damage the power supply.

Instantly Available PC technology enables the boards to enter the ACPI S3 (Suspend-to-RAM)

sleep-state. While in the S3 sleep-state, the computer will appear to be off (the power supply is

off, and the front panel LED is amber if dual colored, or off if single colored.) When signaled by a

wake-up device or event, the system quickly returns to its last known wake state. Table 10 on

page 39 lists the devices and events that can wake the computer from the S3 state.

The boards support the PCI Bus Power Management Interface Specification. Add-in boards that

also support this specification can participate in power management and can be used to wake the

computer.

The use of Instantly Available PC technology requires operating system support and PCI 2.2

compliant add-in cards, PCI Express add-in cards, and drivers.

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Intel D915PCML Datasheet Page 41