Intel Computer Hardware 80200 User Manual

Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureDeveloper’s Manual March, 2003Order Number: 273411-003

x March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureB.4.1 Instruction Cache...

7-22 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.3.4 Registers 8-15: Software DebugSo

Developer’s Manual March, 2003 8-1System Management8This chapter describes the clocking and power management features of the Intel® 80200 processor ba

8-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSystem ManagementThe Intel® 80200 processor supports

Developer’s Manual March, 2003 8-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSystem Management8.2 Processor ResetThe RESET# pin m

8-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSystem Management8.2.2 Reset Effect on OutputsAfter

Developer’s Manual March, 2003 8-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSystem Management8.3 Power ManagementThe Intel® 8020

8-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSystem ManagementThe JTAG clock must be stopped duri

Developer’s Manual March, 2003 9-1Interrupts99.1 IntroductionThe Intel® 80200 processor based on Intel® XScale™ microarchitecture (compliant with the

9-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureInterrupts9.3 Programmer ModelSoftware has access to

Developer’s Manual March, 2003 9-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureInterrupts9.3.1 INTCTLINTCTL is used to specify what

Developer’s Manual March, 2003 xiIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureC.2.2 TAP Pins...

9-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureInterrupts9.3.2 INTSRCThe Interrupt Source register

Developer’s Manual March, 2003 9-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureInterrupts9.3.3 INTSTRSystems may have differing pri

Developer’s Manual March, 2003 10-1External Bus1010.1 General DescriptionThe Intel® 80200 processor based on Intel® XScale™ microarchitecture (complia

10-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal BusAn alternate configuration with a separ

Developer’s Manual March, 2003 10-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.2 Signal DescriptionTable 10-1. Int

10-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.2.1 Request BusThe request bus issue

Developer’s Manual March, 2003 10-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal BusIn addition to the alignment constraint

10-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.2.2 Data BusSome time after a reques

Developer’s Manual March, 2003 10-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.2.3 Critical Word FirstThe CWF signa

xii March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureFigures1-1 Intel® 80200 Processor based on Intel® XS

10-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal BusThere are eight byte enables (BE#) asso

Developer’s Manual March, 2003 10-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.2.5 Multimaster SupportSimple multim

10-10 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal BusA simpler but lower performance method

Developer’s Manual March, 2003 10-11Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.2.6 AbortIf for any reason a reques

10-12 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.2.7 ECCSoftware running on the Inte

Developer’s Manual March, 2003 10-13Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.2.8 Big Endian System Configuration

10-14 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3 ExamplesAll examples assume a 64-

Developer’s Manual March, 2003 10-15Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3.2 Read Burst, No Critical Word Fi

10-16 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3.3 Read Burst, Critical Word First

Developer’s Manual March, 2003 10-17Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3.4 Word WriteFigure 10-7 shows a 3

Developer’s Manual March, 2003 xiiiIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureTables2-1 Multiply with Internal Accumulate Format.

10-18 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3.5 Two Word Coalesced WriteIn Figu

Developer’s Manual March, 2003 10-19Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3.5.1 Write BurstFigure 10-9 shows

10-20 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3.6 Write Burst, CoalescedFigure 10

Developer’s Manual March, 2003 10-21Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3.7 Pipelined AccessesThe example i

10-22 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3.8 Locked AccessAn example of a lo

Developer’s Manual March, 2003 10-23Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3.9 Aborted AccessAs discussed in S

10-24 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureExternal Bus10.3.10 HoldFigure 10-14 shows an exam

Developer’s Manual March, 2003 11-1Bus Controller1111.1 IntroductionThe Intel® 80200 processor based on Intel® XScale™ microarchitecture (compliant wi

11-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureBus Controller11.3 Error HandlingThe BCU is able to

Developer’s Manual March, 2003 11-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureBus Controller11.3.2 ECC ErrorsAn ECC error occurs

xiv March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ Microarchitecture9-1 Interrupt Control Register (CP13 register 0) ...

11-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureBus ControllerError reporting may be enabled with t

Developer’s Manual March, 2003 11-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureBus Controller11.4 Programmer ModelThe BCU register

11-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureBus ControllerBCUCTL.TP allows software to determin

Developer’s Manual March, 2003 11-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureBus ControllerWhen ECC is enabled, the BCU only gen

11-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureBus ControllerBCUMOD.AF affects the behavior of the

Developer’s Manual March, 2003 11-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureBus Controller11.4.2 ECC Error RegistersThe content

11-10 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureBus ControllerThe BCU does not write to these ELOG

Developer’s Manual March, 2003 12-1Performance Monitoring12This chapter describes the performance monitoring facility of the Intel® 80200 processor ba

12-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Monitoring12.2 Clock Counter (CCNT; CP1

Developer’s Manual March, 2003 12-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Monitoring12.3 Performance Count Regist

Developer’s Manual March, 2003 xvIntel® 80200 Processor based on Intel® XScale™ Microarchitecture14-14 Semaphore Instruction Timings ...

12-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Monitoring12.4 Performance Monitor Cont

Developer’s Manual March, 2003 12-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Monitoring12.4.1 Managing PMNCThe follo

12-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Monitoring12.5 Performance Monitoring E

Developer’s Manual March, 2003 12-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance MonitoringSome typical combination of c

12-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Monitoring12.5.2 Data Cache Efficiency

Developer’s Manual March, 2003 12-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Monitoring12.5.4 Data/Bus Request Buffe

12-10 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance MonitoringPMN1 counts the number of wr

Developer’s Manual March, 2003 12-11Intel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Monitoring12.6 Multiple Performance Mo

12-12 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Monitoring12.7 ExamplesIn this example

Developer’s Manual March, 2003 13-1Software Debug13This chapter describes software debug and related features in the Intel® 80200 processor based on I

13-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.3 IntroductionThe Intel® 80200 pro

Developer’s Manual March, 2003 13-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.4 Debug Control and Status Registe

13-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.4.1 Global Enable Bit (GE)The Glob

Developer’s Manual March, 2003 13-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.4.3 Vector Trap Bits (TF,TI,TD,TA,

13-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.5 Debug ExceptionsA debug exceptio

Developer’s Manual March, 2003 13-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware DebugDuring Halt mode, software running on

13-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.5.2 Monitor ModeIn monitor mode, t

Developer’s Manual March, 2003 13-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.6 HW Breakpoint ResourcesThe Intel

13-10 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.6.2 Data BreakpointsThe Intel® 80

Developer’s Manual March, 2003 13-11Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware DebugWhen DBR1 is programmed as a data ad

Developer’s Manual March, 2003 1-1Introduction11.1 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture High-Level OverviewThe Intel® 8020

13-12 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.8 Transmit/Receive Control Regist

Developer’s Manual March, 2003 13-13Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.8.1 RX Register Ready Bit (RR)The

13-14 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.8.2 Overflow Flag (OV)The Overflo

Developer’s Manual March, 2003 13-15Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.8.4 TX Register Ready Bit (TR)The

13-16 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.9 Transmit Register (TX)The TX re

Developer’s Manual March, 2003 13-17Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.11 Debug JTAG AccessThere are fou

13-18 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.11.2 SELDCSR JTAG RegisterPlacing

Developer’s Manual March, 2003 13-19Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.11.2.1 DBG.HLD_RSTThe debugger us

13-20 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.11.2.2 DBG.BRKDBG.BRK allows the

Developer’s Manual March, 2003 13-21Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.11.4 DBGTX JTAG RegisterThe DBGTX

1-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureIntroduction1.1.2 FeaturesFigure 1-1 shows the major

13-22 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.11.6 DBGRX JTAG RegisterThe DBGRX

Developer’s Manual March, 2003 13-23Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.11.6.1 RX Write Logic The RX writ

13-24 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.11.6.2 DBGRX Data RegisterThe bit

Developer’s Manual March, 2003 13-25Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.11.6.4 DBG.VThe debugger sets thi

13-26 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.12 Trace BufferThe 256 entry trac

Developer’s Manual March, 2003 13-27Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware DebugWhen the trace buffer is enabled, re

13-28 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.13 Trace Buffer EntriesTrace buff

Developer’s Manual March, 2003 13-29Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.13.1.1 Exception Message ByteWhen

13-30 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.13.1.2 Non-exception Message Byte

Developer’s Manual March, 2003 13-31Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.13.1.3 Address BytesOnly indirect

Developer’s Manual March, 2003 1-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureIntroduction1.1.2.2 Memory ManagementThe Intel® 8020

13-32 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.13.2 Trace Buffer UsageThe Intel®

Developer’s Manual March, 2003 13-33Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware DebugAs the trace buffer is read, the old

13-34 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.14 Downloading Code in the ICache

Developer’s Manual March, 2003 13-35Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.14.2 LDIC JTAG Data RegisterThe L

13-36 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.14.3 LDIC Cache FunctionsThe Inte

Developer’s Manual March, 2003 13-37Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware DebugAll packets are 33 bits in length. B

13-38 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.14.4 Loading IC During ResetCode

Developer’s Manual March, 2003 13-39Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.14.4.1 Loading IC During Cold Res

13-40 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware DebugAn external host should take the fol

Developer’s Manual March, 2003 13-41Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.14.4.2 Loading IC During a Warm R

ii March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureInformation in this document is provided in connectio

1-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureIntroduction1.1.2.6 Power ManagementThe Intel® 80200

13-42 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware DebugIf it is necessary to download code

Developer’s Manual March, 2003 13-43Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.14.5 Dynamically Loading IC After

13-44 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware DebugThe following steps describe the det

Developer’s Manual March, 2003 13-45Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.14.5.1 Dynamic Code Download Sync

13-46 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.14.6 Mini Instruction Cache Overv

Developer’s Manual March, 2003 13-47Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.15 Halt Mode Software ProtocolThi

13-48 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.15.1.2 Placing the Handler in Mem

Developer’s Manual March, 2003 13-49Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.15.2 Implementing a Debug Handler

13-50 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.15.2.3 Dynamic Debug HandlerOn th

Developer’s Manual March, 2003 13-51Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug2. Using the Main ICThe steps for do

Developer’s Manual March, 2003 1-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureIntroduction1.2 Terminology and Conventions1.2.1 Num

13-52 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.15.2.4 High-Speed DownloadSpecial

Developer’s Manual March, 2003 13-53Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.15.3 Ending a Debug Session Prior

13-54 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureSoftware Debug13.16 Software Debug Notes/Errata1.

Developer’s Manual March, 2003 14-1Performance Considerations14This chapter describes relevant performance considerations that compiler writers, appli

14-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Considerations14.2 Branch PredictionThe

Developer’s Manual March, 2003 14-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Considerations14.4 Instruction Latencie

14-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Considerations• Minimum Resource Latenc

Developer’s Manual March, 2003 14-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Considerations14.4.3 Data Processing In

14-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Considerations14.4.4 Multiply Instructi

Developer’s Manual March, 2003 14-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance ConsiderationsUMULLRs[31:15] = 0x000000

1-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureIntroduction1.3 Other Relevant Documents• Intel® 802

14-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Considerations14.4.5 Saturated Arithmet

Developer’s Manual March, 2003 14-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitecturePerformance Considerations14.4.8 Semaphore Instruct

Developer’s Manual March, 2003 A-1Compatibility: Intel® 80200 Processor vs. SA-110 AThis appendix highlights the differences between the first generat

A-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureCompatibility: Intel® 80200 Processor vs. SA-110Feat

Developer’s Manual March, 2003 A-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureCompatibility: Intel® 80200 Processor vs. SA-110A.3

A-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureCompatibility: Intel® 80200 Processor vs. SA-110A.3.

Developer’s Manual March, 2003 A-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureCompatibility: Intel® 80200 Processor vs. SA-110A.3.

Developer’s Manual March, 2003 B-1Optimization Guide BB.1 IntroductionThis appendix contains optimization techniques for achieving the highest perform

Developer’s Manual March, 2003 2-1Programming Model2This chapter describes the programming model of the Intel® 80200 processor based on Intel® XScale™

B-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.2 Intel® 80200 Processor Pipelin

Developer’s Manual March, 2003 B-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.2.1.2. Intel® 80200 Processor Pi

B-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.2.1.3. Out Of Order CompletionSe

Developer’s Manual March, 2003 B-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.2.2 Instruction Flow Through the

B-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.2.3 Main Execution PipelineB.2.3

Developer’s Manual March, 2003 B-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.2.3.3. RF (Register File / Shift

B-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.2.4 Memory PipelineThe memory pi

Developer’s Manual March, 2003 B-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.3 Basic OptimizationsThis chapte

B-10 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.3.1.2. Optimizing BranchesBranc

Developer’s Manual March, 2003 B-11Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideP2 Percentage of times we are lik

2-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming Model2.2.4 ARM* DSP-Enhanced Instruction

B-12 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.3.1.3. Optimizing Complex Expre

Developer’s Manual March, 2003 B-13Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.3.2 Bit Field ManipulationThe I

B-14 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.3.3 Optimizing the Use of Immed

Developer’s Manual March, 2003 B-15Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.3.4 Optimizing Integer Multiply

B-16 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.3.5 Effective Use of Addressing

Developer’s Manual March, 2003 B-17Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4 Cache and Prefetch Optimizati

B-18 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.1.4. Locking Code into the In

Developer’s Manual March, 2003 B-19Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.2 Data and Mini CacheThe Inte

B-20 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.2.3. Read Allocate and Read-w

Developer’s Manual March, 2003 B-21Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.2.5. Mini-data CacheThe mini-

Developer’s Manual March, 2003 2-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming Model2.3 Extensions to ARM* Architecture

B-22 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.2.6. Data AlignmentCache line

Developer’s Manual March, 2003 B-23Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.2.7. Literal PoolsThe Intel®

B-24 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.3 Cache ConsiderationsB.4.3.1

Developer’s Manual March, 2003 B-25Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.4 Prefetch ConsiderationsThe

B-26 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideThe Intel® 80200 processor needs

Developer’s Manual March, 2003 B-27Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.4.2. Prefetch Loop Scheduling

B-28 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.4.6. Bandwidth LimitationsOve

Developer’s Manual March, 2003 B-29Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.4.7. Cache Memory Considerati

B-30 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization Guideon a 32-byte boundary, modificati

Developer’s Manual March, 2003 B-31Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.4.8. Cache BlockingCache bloc

2-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming Model2.3.1.1 Multiply With Internal Accu

B-32 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.4.10. Pointer PrefetchNot all

Developer’s Manual March, 2003 B-33Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.4.11. Loop InterchangeAs ment

B-34 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.4.4.13. Prefetch to Reduce Regi

Developer’s Manual March, 2003 B-35Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.5 Instruction SchedulingThis ch

B-36 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization Guide; all other registers are in uses

Developer’s Manual March, 2003 B-37Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.5.1.1. Scheduling Load and Stor

B-38 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.5.1.2. Scheduling Load and Stor

Developer’s Manual March, 2003 B-39Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.5.2 Scheduling Data Processing

B-40 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.5.3 Scheduling Multiply Instruc

Developer’s Manual March, 2003 B-41Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.5.4 Scheduling SWP and SWPB Ins

Developer’s Manual March, 2003 2-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming ModelMIA does not support unsigned multi

B-42 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.5.5 Scheduling the MRA and MAR

Developer’s Manual March, 2003 B-43Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.5.6 Scheduling the MIA and MIAP

B-44 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.5.7 Scheduling MRS and MSR Inst

Developer’s Manual March, 2003 B-45Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureOptimization GuideB.6 Optimizing C LibrariesMany of

Developer’s Manual March, 2003 C-1Test Features CThe Intel® 80200 processor based on Intel® XScale™ microarchitecture (compliant with the ARM* Archite

C-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesC.2.1 Boundary Scan ArchitectureBoundar

Developer’s Manual March, 2003 C-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesC.2.2 TAP PinsThe Intel® 80200 processo

C-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesC.2.3 Instruction Register (IR)The inst

Developer’s Manual March, 2003 C-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesTable C-3. IEEE InstructionsInstructio

2-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming ModelThe MIAxy instruction performs one1

C-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesC.2.4 TAP Test Data RegistersThe Intel®

Developer’s Manual March, 2003 C-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesC.2.5 TAP ControllerThe TAP controller

C-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesC.2.5.1. Test Logic Reset StateIn this

Developer’s Manual March, 2003 C-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesC.2.5.5. Shift-DR StateIn this controll

C-10 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesC.2.5.9. Update-DR StateThe Boundary-S

Developer’s Manual March, 2003 C-11Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesC.2.5.13. Exit1-IR StateThis is a temp

C-12 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesC.2.5.17. Boundary-Scan ExampleIn the

Developer’s Manual March, 2003 C-13Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesFigure C-3. JTAG Example0001100000000

C-14 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesFigure C-4. Timing Diagram Illustrati

Developer’s Manual March, 2003 C-15Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureTest FeaturesFigure C-5. Timing Diagram Illustrati

Developer’s Manual March, 2003 2-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming Model2.3.1.2 Internal Accumulator Access

Developer’s Manual March, 2003 iiiIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureContents1 Introduction ...

2-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming ModelThe MAR instruction moves the value

Developer’s Manual March, 2003 2-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming Model2.3.2 New Page AttributesThe Intel®

2-10 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming ModelThe P bit controls ECC.The TEX (Ty

Developer’s Manual March, 2003 2-11Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming Model2.3.3 Additions to CP15 Functional

2-12 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming Model2.3.4 Event Architecture2.3.4.1 Ex

Developer’s Manual March, 2003 2-13Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming Model2.3.4.3 Prefetch AbortsThe Intel®

2-14 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming Model2.3.4.4 Data AbortsTwo types of da

Developer’s Manual March, 2003 2-15Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming ModelImprecise data aborts• A data cach

2-16 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureProgramming ModelMultiple Data AbortsMultiple data

Developer’s Manual March, 2003 3-1Memory Management3This chapter describes the memory management unit implemented in the Intel® 80200 processor based

iv March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ Microarchitecture3.2.2.1 Page (P) Attribute Bit...

3-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureMemory Management3.2 Architecture Model3.2.1 Version

Developer’s Manual March, 2003 3-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureMemory Management3.2.2.4 Data Cache and Write Buffer

3-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureMemory Management3.2.2.5 Details on Data Cache and W

Developer’s Manual March, 2003 3-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureMemory Management3.3 Interaction of the MMU, Instruc

3-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureMemory Management3.4 Control3.4.1 Invalidate (Flush)

Developer’s Manual March, 2003 3-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureMemory Management3.4.3 Locking EntriesIndividual ent

3-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureMemory ManagementNote: Care must be exercised here w

Developer’s Manual March, 2003 3-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureMemory Management3.4.4 Round-Robin Replacement Algor

Developer’s Manual March, 2003 4-1Instruction Cache4The Intel® 80200 processor based on Intel® XScale™ microarchitecture (compliant with the ARM* Arch

Developer’s Manual March, 2003 vIntel® 80200 Processor based on Intel® XScale™ Microarchitecture6.2.3.3 Write Miss Policy ...

4-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureInstruction Cache4.2 Operation4.2.1 Operation When I

Developer’s Manual March, 2003 4-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureInstruction Cache4.2.3 Fetch PolicyAn instruction-ca

4-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureInstruction Cache4.2.5 Parity ProtectionThe instruct

Developer’s Manual March, 2003 4-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureInstruction Cache4.2.6 Instruction Fetch LatencyBeca

4-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureInstruction Cache4.3 Instruction Cache Control4.3.1

Developer’s Manual March, 2003 4-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureInstruction Cache4.3.3 Invalidating the Instruction

4-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureInstruction Cache4.3.4 Locking Instructions in the I

Developer’s Manual March, 2003 4-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureInstruction CacheSoftware can lock down several diff

Developer’s Manual March, 2003 5-1Branch Target Buffer5Intel® 80200 processor based on Intel® XScale™ microarchitecture (compliant with the ARM* Archi

vi March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ Microarchitecture9.3 Programmer Model...

5-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureBranch Target Buffer5.1.1 ResetAfter Processor Reset

Developer’s Manual March, 2003 5-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureBranch Target Buffer5.2 BTB Control5.2.1 Disabling/E

Developer’s Manual March, 2003 6-1Data Cache6The Intel® 80200 processor based on Intel® XScale™ microarchitecture (compliant with the ARM* Architectur

6-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureData CacheFigure 6-1. Data Cache Organizationway 0w

Developer’s Manual March, 2003 6-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureData Cache6.1.2 Mini-Data Cache OverviewThe mini-dat

6-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureData Cache6.1.3 Write Buffer and Fill Buffer Overvie

Developer’s Manual March, 2003 6-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureData Cache6.2 Data Cache and Mini-Data Cache Operati

6-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureData Cache6.2.3.2 Read Miss PolicyThe following sequ

Developer’s Manual March, 2003 6-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureData Cache6.2.3.3 Write Miss PolicyA write operation

Developer’s Manual March, 2003 viiIntel® 80200 Processor based on Intel® XScale™ Microarchitecture12.5.3 Instruction Fetch Latency Mode...

6-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureData Cache6.2.4 Round-Robin Replacement AlgorithmThe

Developer’s Manual March, 2003 6-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureData Cache6.3 Data Cache and Mini-Data Cache Control

6-10 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureData Cache6.3.3.1 Global Clean and Invalidate Opera

Developer’s Manual March, 2003 6-11Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureData CacheThe line-allocate command will not operat

6-12 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureData Cache6.4 Re-configuring the Data Cache as Data

Developer’s Manual March, 2003 6-13Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureData CacheExample 6-3. Locking Data into the Data C

6-14 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureData CacheExample 6-4. Creating Data RAM; R1 conta

Developer’s Manual March, 2003 6-15Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureData CacheTags can be locked into the data cache by

6-16 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureData Cache6.5 Write Buffer/Fill Buffer Operation an

Developer’s Manual March, 2003 7-1Configuration7This chapter describes the System Control Coprocessor (CP15) and coprocessor 14 (CP14). CP15 configure

viii March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ Microarchitecture13.11.6.4 DBG.V ...

7-2 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfigurationThe format of MRC and MCR is shown in T

Developer’s Manual March, 2003 7-3Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfigurationThe format of LDC and STC is shown in T

7-4 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2 CP15 RegistersTable 7-3 lists the C

Developer’s Manual March, 2003 7-5Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.1 Register 0: ID and Cache Type Reg

7-6 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration5:3 Read / Write Ignored Instruction ca

Developer’s Manual March, 2003 7-7Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.2 Register 1: Control and Auxiliary

7-8 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfigurationThe mini-data cache attribute bits, in

Developer’s Manual March, 2003 7-9Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.3 Register 2: Translation Table Bas

7-10 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.6 Register 5: Fault Status Registe

Developer’s Manual March, 2003 7-11Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.8 Register 7: Cache FunctionsAll t

Developer’s Manual March, 2003 ixIntel® 80200 Processor based on Intel® XScale™ Microarchitecture14.4.10 Miscellaneous Instruction Timing...

7-12 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfigurationOther items to note about the line-all

Developer’s Manual March, 2003 7-13Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.9 Register 8: TLB OperationsDisabl

7-14 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.10 Register 9: Cache Lock DownRegi

Developer’s Manual March, 2003 7-15Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.11 Register 10: TLB Lock DownRegis

7-16 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.13 Register 13: Process IDThe Inte

Developer’s Manual March, 2003 7-17Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.14 Register 14: Breakpoint Registe

7-18 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.2.15 Register 15: Coprocessor Access

Developer’s Manual March, 2003 7-19Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfigurationTable 7-20. Coprocessor Access Regist

7-20 March, 2003 Developer’s ManualIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.3 CP14 RegistersTable 7-21 lists the

Developer’s Manual March, 2003 7-21Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureConfiguration7.3.3 Registers 6-7: Clock and Power M