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Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Datasheet 13
Introduction
1.6 Reference Documents
The reader of this specification should also be familiar with material and concepts
presented in the following documents:
Note: Contact your Intel representative or check http://developer.intel.com for the latest
revision of the reference documents.
§
Intel
®
Itanium
®
2 Processor Specification Update
Intel
®
Itanium
®
Architecture Software Developer’s Manual, Volume 1:
Application Architecture
Intel
®
Itanium
®
Architecture Software Developer’s Manual, Volume 2: System
Architecture
Intel
®
Itanium
®
Architecture Software Developer’s Manual,
Volume 3: Instruction Set Reference
Intel
®
Itanium
®
2 Processor Reference Manual for Software Development and
Optimization
Intel
®
Itanium
®
Processor Family System Abstraction Layer Specification
ITP700 Debug Port Design Guide
System Management Bus Specification
- Dual-Core Intel 1
- Itanium 1
- Processor 1
- 9000 and 9100 Series 1
- Contents 3
- 4 Dual-Core Intel 4
- 6 Dual-Core Intel 6
- Revision History 8
- Processor 9000 and 9
- 9100 Series 9
- Product Features 9
- 10 Dual-Core Intel 10
- 1 Introduction 11
- Cache Sizes 12
- 1.4 Terminology 12
- 1.5 State of Data 12
- 1.6 Reference Documents 13
- 14 Dual-Core Intel 14
- Introduction 14
- 2 Electrical Specifications 15
- 2.2.2 Signal Descriptions 17
- 2.3 Package Specifications 18
- 2.4 Signal Specifications 18
- 2.4.1 Maximum Ratings 22
- Measurement Guidelines 23
- 2.5.3 Activity Factor 24
- Specifications 25
- 2.5.6 Wired-OR Signals 25
- Electrical Specifications 31
- 32 Dual-Core Intel 32
- 3 Pinout Specifications 35
- 4 Mechanical Specifications 65
- Figure 4-1. Processor Package 66
- Mechanical Specifications 67
- 68 Dual-Core Intel 68
- 4.2 Package Marking 72
- 74 Dual-Core Intel 74
- 5 Thermal Specifications 75
- 5.2 Case Temperature 76
- Thermocouple Location 77
- 78 Dual-Core Intel 78
- Thermal Specifications 78
- 6 System Management Feature 79
- System Board 80
- 6.1.3 SMBus Device Addressing 81
- 6.2 Processor Information ROM 82
- Byte Present 84
- 6.3 Scratch EEPROM 85
- Supported SMBus Transactions 85
- 6.5 Thermal Sensing Device 86
- Transactions 87
- 6.7.2 Thermal Limit Registers 89
- 6.7.3 Status Register 89
- 6.7.4 Configuration Register 89
- A Signals Reference 91
- A.1.6 ATTR[3:0]# (I/O) 92
- A.1.7 BCLKp/BCLKn (I) 92
- A.1.8 BE[7:0]# (I/O) 92
- A.1.9 BERR# (I/O) 93
- A.1.10 BINIT# (I/O) 94
- A.1.11 BNR# (I/O) 94
- A.1.12 BPM[5:0]# (I/O) 94
- A.1.13 BPRI# (I) 94
- A.1.15 BREQ[3:0]# (I/O) 95
- 96 Dual-Core Intel 96
- A.1.24 DEN# (I/O) 97
- A.1.25 DEP[15:0]# (I/O) 97
- A.1.26 DHIT# (I) 97
- A.1.45 LOCK# (I/O) 100
- A.1.41 INT (I) 100
- A.1.42 IP[1:0]# (I) 100
- A.1.43 LEN[2:0]# (I/O) 100
- A.1.44 LINT[1:0] (I) 100
- A.1.46 NMI (I) 101
- A.1.47 OWN# (I/O) 101
- A.1.48 PMI# (I) 101
- A.1.49 PWRGOOD (I) 101
- A.1.50 REQ[5:0]# (I/O) 101
- A.1.51 RESET# (I) 102
- A.1.52 RP# (I/O) 102
- Signals Reference 103
- A.2 Signal Summaries 105
- 108 Dual-Core Intel 108
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