Intel core 2 Duo T5850 Specifications Page 1

Document Number: 252046-026Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual Documentation ChangesDecember 2009Notice: The Intel® 64 and IA

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 10Documentation Changes3.1.1.4 64-bit Mode Column in the Instruc

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 100Documentation ChangesMOVNTPS—Store Packed Single-Precision Floa

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 101Documentation ChangesMOVQ—Move QuadwordInstruction Operand Enco

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 102Documentation ChangesMOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data fro

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 103Documentation ChangesMOVSD—Move Scalar Double-Precision Floatin

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 104Documentation ChangesMOVSLDUP—Move Packed Single-FP Low and Dup

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 105Documentation ChangesMOVSX/MOVSXD—Move with Sign-ExtensionInstr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 106Documentation ChangesMOVUPD—Move Unaligned Packed Double-Precis

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 107Documentation ChangesMOVZX—Move with Zero-ExtendInstruction Ope

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 108Documentation ChangesMUL—Unsigned MultiplyInstruction Operand E

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 109Documentation ChangesMULPS—Multiply Packed Single-Precision Flo

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 11Documentation ChangesAAA—ASCII Adjust After AdditionInstruction

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 110Documentation ChangesMWAIT—Monitor WaitInstruction Operand Enco

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 111Documentation ChangesInstruction Operand Encoding...NOP—No Oper

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 112Documentation ChangesOR—Logical Inclusive ORInstruction Operand

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 113Documentation ChangesORPD—Bitwise Logical OR of Double-Precisio

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 114Documentation ChangesInstruction Operand Encoding...IA-32 Archi

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 115Documentation ChangesInstruction Operand Encoding...IA-32 Archi

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 116Documentation ChangesPACKSSWB/PACKSSDW—Pack with Signed Saturat

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 117Documentation ChangesPACKUSDW — Pack with Unsigned SaturationIn

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 118Documentation ChangesPADDB/PADDW/PADDD—Add Packed IntegersInstr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 119Documentation ChangesPADDSB/PADDSW—Add Packed Signed Integers w

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 12Documentation ChangesAAS—ASCII Adjust AL After SubtractionInstru

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 120Documentation ChangesInstruction Operand Encoding...PALIGNR — P

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 121Documentation ChangesPANDN—Logical AND NOTInstruction Operand E

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 122Documentation ChangesInstruction Operand Encoding...PBLENDVB —

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 123Documentation ChangesPCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Da

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 124Documentation ChangesPCMPESTRI — Packed Compare Explicit Length

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 125Documentation ChangesPCMPISTRM — Packed Compare Implicit Length

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 126Documentation ChangesPCMPGTQ — Compare Packed Data for Greater

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 127Documentation ChangesIn 64-bit mode, using a REX prefix in the

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 128Documentation ChangesInstruction Operand Encoding...PHADDSW — P

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 129Documentation ChangesPHSUBW/PHSUBD — Packed Horizontal Subtract

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 13Documentation ChangesInstruction Operand Encoding...ADD—AddOpcod

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 130Documentation ChangesPINSRB/PINSRD/PINSRQ — Insert Byte/Dword/Q

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 131Documentation ChangesPMADDUBSW — Multiply and Add Packed Signed

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 132Documentation ChangesPMAXSB — Maximum of Packed Signed Byte Int

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 133Documentation ChangesInstruction Operand Encoding...PMAXUB—Maxi

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 134Documentation ChangesPMAXUW — Maximum of Packed Word IntegersIn

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 135Documentation ChangesPMINSW—Minimum of Packed Signed Word Integ

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 136Documentation ChangesPMINUD — Minimum of Packed Dword IntegersI

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 137Documentation ChangesPMINUW — Minimum of Packed Word IntegersIn

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 138Documentation ChangesPMOVSX — Packed Move with Sign ExtendInstr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 139Documentation ChangesPMOVZX — Packed Move with Zero ExtendInstr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 14Documentation ChangesInstruction Operand Encoding...ADDPD—Add Pa

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 140Documentation ChangesPMULHRSW — Packed Multiply High with Round

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 141Documentation ChangesPMULHW—Multiply Packed Signed Integers and

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 142Documentation ChangesPMULLW—Multiply Packed Signed Integers and

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 143Documentation ChangesPOP—Pop a Value from the StackOpcode Instr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 144Documentation ChangesInstruction Operand Encoding...POPA/POPAD—

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 145Documentation ChangesPOPF/POPFD/POPFQ—Pop Stack into EFLAGS Reg

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 146Documentation ChangesPREFETCHh—Prefetch Data Into CachesInstruc

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 147Documentation ChangesInstruction Operand Encoding...PSHUFB — Pa

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 148Documentation ChangesPSHUFHW—Shuffle Packed High WordsInstructi

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 149Documentation ChangesPSIGNB/PSIGNW/PSIGND — Packed SIGN Instruc

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 15Documentation ChangesADDPS—Add Packed Single-Precision Floating-

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 150Documentation ChangesPSLLDQ—Shift Double Quadword Left LogicalI

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 151Documentation ChangesInstruction Operand Encoding...PSRAW/PSRAD

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 152Documentation ChangesInstruction Operand Encoding...PSRLDQ—Shif

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 153Documentation ChangesInstruction Operand Encoding...PSUBB/PSUBW

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 154Documentation ChangesInstruction Operand Encoding...PSUBQ—Subtr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 155Documentation ChangesInstruction Operand Encoding...PSUBUSB/PSU

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 156Documentation ChangesPTEST- Logical CompareInstruction Operand

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 157Documentation ChangesPUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—U

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 158Documentation ChangesPUSH—Push Word, Doubleword or Quadword Ont

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 159Documentation ChangesInstruction Operand Encoding...PUSHA/PUSHA

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 16Documentation ChangesADDSUBPD—Packed Double-FP Add/SubtractInstr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 160Documentation ChangesPXOR—Logical Exclusive ORInstruction Opera

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 161Documentation ChangesOpcode** Instruction Op/ En64-Bit ModeComp

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 162Documentation ChangesOpcode** Instruction Op/ En64-Bit ModeComp

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 163Documentation ChangesInstruction Operand Encoding...RCPPS—Compu

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 164Documentation ChangesRCPSS—Compute Reciprocal of Scalar Single-

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 165Documentation ChangesInstruction Operand EncodingDescriptionThe

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 166Documentation ChangesThe Pentium 4 and Intel Xeon processors al

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 167Documentation ChangesThe performance-monitoring counters are ev

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 168Documentation ChangesELSE (* ECX is not valid or CR4.PCE is 0 a

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 169Documentation ChangesRDTSC—Read Time-Stamp CounterInstruction O

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 17Documentation ChangesInstruction Operand Encoding...Opcode Instr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 170Documentation ChangesRDTSCP—Read Time-Stamp Counter and Process

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 171Documentation ChangesF3 REX.W 6F REP OUTS DX, r/m32A Valid N.E.

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 172Documentation ChangesInstruction Operand Encoding...RET—Return

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 173Documentation ChangesInstruction Operand Encoding...ROUNDPD — R

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 174Documentation ChangesROUNDSD — Round Scalar Double Precision Fl

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 175Documentation ChangesRSQRTPS—Compute Reciprocals of Square Root

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 176Documentation ChangesInstruction Operand Encoding...SAL/SAR/SHL

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 177Documentation ChangesOpcode Instruction Op/ En64-Bit ModeCompat

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 178Documentation ChangesInstruction Operand Encoding...Opcode*** I

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 179Documentation ChangesSBB—Integer Subtraction with BorrowOpcode

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 18Documentation ChangesANDPD—Bitwise Logical AND of Packed Double-

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 180Documentation ChangesInstruction Operand Encoding...SCAS/SCASB/

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 181Documentation ChangesInstruction Operand Encoding...SETcc—Set B

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 182Documentation ChangesREX + 0F 9E SETLE r/m8* A Valid N.E. Set b

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 183Documentation ChangesInstruction Operand Encoding...SFENCE—Stor

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 184Documentation ChangesDescriptionPerforms a serializing operatio

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 185Documentation ChangesInstruction Operand Encoding...SHRD—Double

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 186Documentation ChangesSHUFPD—Shuffle Packed Double-Precision Flo

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 187Documentation ChangesSLDT—Store Local Descriptor Table Register

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 188Documentation ChangesInstruction Operand Encoding...SQRTPS—Comp

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 189Documentation ChangesSQRTSS—Compute Square Root of Scalar Singl

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 19Documentation ChangesANDNPS—Bitwise Logical AND NOT of Packed Si

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 190Documentation ChangesSTI—Set Interrupt FlagInstruction Operand

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 191Documentation ChangesInstruction Operand Encoding...STR—Store T

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 192Documentation ChangesSUB—SubtractOpcode Instruction Op/ En64-Bi

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 193Documentation ChangesInstruction Operand Encoding...SUBPD—Subtr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 194Documentation ChangesSUBSD—Subtract Scalar Double-Precision Flo

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 195Documentation ChangesSYSCALL—Fast System CallInstruction Operan

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 196Documentation ChangesSS.BASE ← 0; (* Flat segment *)SS.LIMIT ←

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 197Documentation ChangesTEST—Logical CompareOpcode Instruction Op/

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 198Documentation ChangesInstruction Operand Encoding...UCOMISD—Uno

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 199Documentation ChangesUD2—Undefined InstructionInstruction Opera

2Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation ChangesLegal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDE

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 20Documentation ChangesSee “Checking Caller Access Privileges” in

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 200Documentation ChangesUNPCKLPD—Unpack and Interleave Low Packed

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 201Documentation ChangesInstruction Operand Encoding...WAIT/FWAIT—

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 202Documentation ChangesWRMSR—Write to Model Specific RegisterInst

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 203Documentation ChangesXCHG—Exchange Register/Memory with Registe

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 204Documentation ChangesXGETBV—Get Value of Extended Control Regis

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 205Documentation ChangesXOR—Logical Exclusive OROpcode Instruction

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 206Documentation ChangesInstruction Operand Encoding...XORPD—Bitwi

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 207Documentation ChangesXRSTOR—Restore Processor Extended StatesIn

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 208Documentation Changes3. Updates to Chapter 4, Volume 3AChange b

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 209Documentation Changes• PAT: page-attribute table.If CPUID.01H:E

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 21Documentation ChangesBLENDVPD — Variable Blend Packed Double Pre

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 210Documentation Changessaid to reference the other paging structu

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 211Documentation ChangesPaging structures are given different name

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 212Documentation ChangesThe page-directory-pointer-table comprises

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 213Documentation Changes...Table 4-8. Format of a PAE Page-Direct

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 214Documentation Changes4.5 IA-32E PAGINGA logical processor uses

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 215Documentation ChangesBecause a PDPTE is identified using bits 4

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 216Documentation Changes— Bits 51:30 are from the PDPTE.— Bits 29:

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 217Documentation Changes— Bits 51:12 are from the PDPTE.— Bits 11:

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 218Documentation ChangesFigure 4-11. Formats of CR3 and Paging-St

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 219Documentation Changes4.7 PAGE-FAULT EXCEPTIONSAccesses using li

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 22Documentation ChangesBOUND—Check Array Index Against BoundsInstr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 220Documentation ChangesThe PAT is a 64-bit MSR (IA32_PAT; MSR ind

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 221Documentation Changes— If the translation does use a PTE, the p

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 222Documentation Changeswhile the lower bits come from the linear

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 223Documentation Changes• PDPTE cache (IA-32e paging only).1 Each

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 224Documentation Changes• If the nature of the paging structures i

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 225Documentation Changes• If a paging-structure entry is modified

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 226Documentation ChangesIn some cases, the consequences of delayed

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 227Documentation Changes4. Updates to Chapter 5, Volume 3AChange b

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 228Documentation Changesby privilege level 0 operating system or e

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 229Documentation Changes5. Updates to Chapter 8, Volume 3AChange b

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 23Documentation ChangesBSWAP—Byte SwapInstruction Operand Encoding

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 230Documentation Changes• Unaligned 16-, 32-, and 64-bit accesses

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 231Documentation ChangesSoftware should access semaphores (shared

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 232Documentation ChangesExecute a serializing instruction; (* For

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 233Documentation Changesautomatically prevents two or more process

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 234Documentation Changes• LFENCE instructions cannot pass earlier

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 235Documentation Changes• The page attribute table (PAT) can be us

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 236Documentation Changesapplied to an address range dedicated to m

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 237Documentation Changes• Privileged serializing instructions — IN

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 238Documentation Changes1. Waits on the BIOS initialization Lock S

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 239Documentation Changes6. Updates to Chapter 10, Volume 3AChange

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 24Documentation ChangesBTC—Bit Test and ComplementInstruction Oper

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 240Documentation ChangesNOTEIn processors based on Intel Microarch

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 241Documentation Changes...FEE0 01F0H Trigger Mode Register (TMR);

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 242Documentation ChangesSuppress EOI-broadcastsIndicates whether s

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 243Documentation Changesthermal monitor register and its associate

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 244Documentation Changeswhen the local APIC sets one of the error

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 245Documentation Changes...10.5.4 APIC TimerThe local APIC unit co

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 246Documentation Changes...10.6.1 Interrupt Command Register (

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 247Documentation Changes— Destination Mode — Selects one of two de

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 248Documentation ChangesUpon receiving and EOI, the APIC clears th

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 249Documentation Changespriority level is established when the MOV

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 25Documentation ChangesInstruction Operand Encoding...BTS—Bit Test

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 250Documentation ChangesNOTEDo not program an LVT or IOAPIC RTE wi

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 251Documentation Changes• Uses MSR programming interface to access

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 252Documentation Changeseach register is available on the page ref

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 253Documentation Changes815H 150H ISR bits 191:160 Read-only816H 1

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 254Documentation Changes10.12.1.3 Reserved Bit CheckingSection 10

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 255Documentation Changes10.12.2 x2APIC Register AvailabilityThe l

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 256Documentation Changes10.12.5 x2APIC State TransitionsThis sect

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 257Documentation Changesenumerating topology. The presence of CPUI

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 258Documentation Changes10.12.9 ICR Operation in x2APIC ModeIn x2

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 259Documentation Changes10.12.10 Determining IPI Destination in x2

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 26Documentation ChangesInstruction Operand Encoding...Opcode Instr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 260Documentation Changes10.12.10.2 Deriving Logical x2APIC ID fro

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 261Documentation Changes7. Updates to Chapter 15, Volume 3AChange

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 262Documentation Changes8. Updates to Chapter 21, Volume 3BChange

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 263Documentation ChangesThe VMPTRST instruction stores the address

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 264Documentation Changes...21.10 SOFTWARE USE OF THE VMCS AND REL

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 265Documentation Changesdata of an active VMCS on the processor an

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 266Documentation ChangesThe following software usage is consistent

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 267Documentation Changes9. Updates to Chapter 22, Volume 3BChange

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 268Documentation Changes10. Updates to Chapter 25, Volume 3BChange

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 269Documentation Changes— Bits 63:52 are all 0.— Bits 51:30 are fr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 27Documentation ChangesBW/CWDE/CDQE—Convert Byte to Word/Convert W

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 270Documentation Changes11. Updates to Chapter 27, Volume 3BChange

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 271Documentation ChangesVMCS data cached by the processor are flus

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 272Documentation Changes12. Updates to Chapter 30, Volume 3BChange

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 273Documentation Changesthe IA32_PEBS_ENABLE register for the resp

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 274Documentation Changes13. Updates to Appendix A, Volume 3BChange

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 275Documentation ChangesTable A-2 Non-Architectural Performance

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 276Documentation ChangesNon-architectural Performance monitoring e

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 277Documentation ChangesNon-Architectural Performance Events In Ne

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 278Documentation Changes0CH 04H UNC_GQ_SNOOP.GOTO_S_HIT_MCounts th

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 279Documentation Changes33H 07H UNC_QHL_FRC_ACK_CNFLTS.ANYCounts n

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 28Documentation ChangesCLFLUSH—Flush Cache LineInstruction Operand

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 280Documentation Changes35H 02H UNC_ADDR_OPCODE_MATCH.REMOTECounts

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 281Documentation Changes81H 02H UNC_THERMAL_THROTTLED_TEMP.CORE_1C

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 282Documentation Changes...Table A-7 Fixed-Function Performance

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 283Documentation Changes14. Updates to Appendix B, Volume 3BChange

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 284Documentation ChangesTable B-2. IA-32 Architectural MSRsRegist

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 285Documentation ChangesRegister Address Architectural MSR Name an

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 286Documentation Changes...Register Address Architectural MSR Name

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 287Documentation ChangesTable B-5 MSRs in Processors Based on In

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 288Documentation ChangesRegister Address Register NameScopeBit Des

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 289Documentation ChangesRegister Address Register NameScopeBit Des

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 29Documentation ChangesCLI — Clear Interrupt FlagInstruction Opera

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 290Documentation ChangesRegister Address Register NameScopeBit Des

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 291Documentation ChangesB-5 MSRS IN THE NEXT GENERATION INTEL PRO

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 292Documentation Changes15. Updates to Appendix G, Volume 3BChange

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 3ContentsRevision History . . . . . . . . . . . . . . . . . . . .

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 30Documentation ChangesCMOVcc—Conditional MoveOpcode Instruction O

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 31Documentation ChangesOpcode Instruction Op/ En64-Bit ModeCompat/

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 32Documentation ChangesOpcode Instruction Op/ En64-Bit ModeCompat/

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 33Documentation ChangesInstruction Operand Encoding...CMP—Compare

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 34Documentation ChangesInstruction Operand Encoding...Opcode Instr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 35Documentation ChangesCMPPD—Compare Packed Double-Precision Float

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 36Documentation ChangesCMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 37Documentation ChangesInstruction Operand Encoding...CMPSD—Compar

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 38Documentation ChangesCMPSS—Compare Scalar Single-Precision Float

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 39Documentation ChangesCMPXCHG—Compare and ExchangeInstruction Ope

Revision History4Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation ChangesRevision HistoryRevision Description Date-001• Ini

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 40Documentation ChangesCMPXCHG8B/CMPXCHG16B—Compare and Exchange B

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 41Documentation ChangesCOMISS—Compare Scalar Ordered Single-Precis

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 42Documentation ChangesTable 3-20. Information Returned by CPUID

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 43Documentation ChangesCRC32 — Accumulate CRC32 ValueInstruction O

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 44Documentation ChangesCVTDQ2PS—Convert Packed Dword Integers to P

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 45Documentation ChangesInstruction Operand Encoding...CVTPD2PS—Con

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 46Documentation ChangesCVTPI2PS—Convert Packed Dword Integers to P

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 47Documentation ChangesInstruction Operand Encoding...CVTPS2PI—Con

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 48Documentation ChangesCVTSD2SS—Convert Scalar Double-Precision FP

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 49Documentation ChangesCVTSI2SS—Convert Dword Integer to Scalar Si

Revision HistoryIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 5§-024• Removed Documentation Changes 1-21• Added

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 50Documentation ChangesInstruction Operand Encoding...CVTTPD2DQ—Co

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 51Documentation ChangesCVTTPS2DQ—Convert with Truncation Packed Si

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 52Documentation ChangesCVTTSD2SI—Convert with Truncation Scalar Do

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 53Documentation ChangesCWD/CDQ/CQO—Convert Word to Doubleword/Conv

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 54Documentation ChangesDEC—Decrement by 1Instruction Operand Encod

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 55Documentation ChangesInstruction Operand Encoding...DIVPD—Divide

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 56Documentation ChangesInstruction Operand Encoding...DIVSS—Divide

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 57Documentation ChangesDPPS — Dot Product of Packed Single Precisi

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 58Documentation ChangesEXTRACTPS — Extract Packed Single Precision

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 59Documentation ChangesFXRSTOR—Restore x87 FPU, MMX , XMM, and MXC

Revision History6Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 60Documentation ChangesHADDPS—Packed Single-FP Horizontal AddInstr

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 61Documentation ChangesInstruction Operand Encoding...IDIV—Signed

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 62Documentation ChangesIMUL—Signed MultiplyInstruction Operand Enc

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 63Documentation ChangesIN—Input from PortInstruction Operand Encod

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 64Documentation ChangesInstruction Operand Encoding...INS/INSB/INS

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 65Documentation ChangesINSERTPS — Insert Packed Single Precision F

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 66Documentation ChangesIF (VM = 1 and IOPL < 3 AND INT n) THEN

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 67Documentation ChangesFI;IF software interrupt (* Generated by IN

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 68Documentation ChangesINVD—Invalidate Internal CachesInstruction

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 69Documentation ChangesJcc—Jump if Condition Is MetOpcode Instruct

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 7PrefacePrefaceThis document is an update to the specifications co

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 70Documentation Changes71 cb JNO rel8 A Valid Valid Jump short if

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 71Documentation Changes0F 84 cd JE rel32 A Valid Valid Jump near i

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 72Documentation Changes0F 87 cd JNBE rel32 A Valid Valid Jump near

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 73Documentation ChangesInstruction Operand Encoding...0F 89 cw JNS

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 74Documentation ChangesJMP—JumpInstruction Operand Encoding...Opco

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 75Documentation ChangesLAHF—Load Status Flags into AH RegisterInst

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 76Documentation ChangesLDDQU—Load Unaligned Integer 128 BitsInstru

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 77Documentation ChangesLDS/LES/LFS/LGS/LSS—Load Far PointerInstruc

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 78Documentation ChangesLEA—Load Effective AddressInstruction Opera

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 79Documentation ChangesLGDT/LIDT—Load Global/Interrupt Descriptor

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 8Summary Tables of ChangesSummary Tables of ChangesThe following t

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 80Documentation ChangesLOCK—Assert LOCK# Signal PrefixInstruction

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 81Documentation ChangesLODS/LODSB/LODSW/LODSD/LODSQ—Load StringIns

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 82Documentation ChangesLOOP/LOOPcc—Loop According to ECX CounterIn

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 83Documentation ChangesLTR—Load Task RegisterInstruction Operand E

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 84Documentation ChangesMASKMOVQ—Store Selected Bytes of QuadwordIn

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 85Documentation ChangesMAXSD—Return Maximum Scalar Double-Precisio

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 86Documentation Changesany serializing instructions (such as the C

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 87Documentation ChangesMINPS—Return Minimum Packed Single-Precisio

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 88Documentation ChangesMONITOR—Set Up Monitor AddressInstruction O

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 89Documentation ChangesOpcode Instruction Op/ En64-Bit ModeCompat/

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 9Documentation ChangesDocumentation Changes1. Updates to Chapter 3

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 90Documentation ChangesInstruction Operand Encoding...MOV—Move to/

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 91Documentation ChangesMOV—Move to/from Debug RegistersInstruction

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 92Documentation ChangesMOVAPS—Move Aligned Packed Single-Precision

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 93Documentation ChangesMOVD/MOVQ—Move Doubleword/Move QuadwordInst

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 94Documentation ChangesMOVDQA—Move Aligned Double QuadwordInstruct

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 95Documentation ChangesMOVHLPS— Move Packed Single-Precision Float

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 96Documentation ChangesMOVHPS—Move High Packed Single-Precision Fl

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 97Documentation ChangesMOVLPD—Move Low Packed Double-Precision Flo

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 98Documentation ChangesMOVMSKPD—Extract Packed Double-Precision Fl

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 99Documentation ChangesMOVNTDQ—Store Double Quadword Using Non-Tem