Intel LE80535VC600512 Datasheet Page 38

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Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
Datasheet 283654-003 38
Figure 13. Quick Start/Deep Sleep Timing
T
w
stpgnt
Running
Running
BCLK
STPCLK#
CPU bus
SLP#
Compatibility
Signals
Changing
Normal Quick Start Deep Sleep
Quick Start
Normal
Frozen
T
v
T
y
T
z
T
x
V0010-00
NOTES:
T
v
= T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay)
T
w
= T46 (Setup Time to Input Signal Hold Requirement)
T
x
= T47 (Deep Sleep PLL Lock Latency)
T
y
= T48 (PLL lock to STPCLK# Hold Time)
T
z
= T49 (Input Signal Hold Time)
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