Intel L5618 Datasheet Page 56
- Page / 64
- Table of contents
- BOOKMARKS
- Processor 5600 Series 1
- Contents 3
- Revision History 6
- 1 Introduction 7
- Introduction 8
- 2 Register Description 9
- 2.3 Device Mapping 11
- Control Registers 25
- Address Registers 26
- Rank Registers 27
- Thermal Control Registers 28
- 2.5 PCI Standard Registers 36
- 2.6.1 DESIRED_CORES 37
- 2.6.2 MIRROR_PORT_CTL 38
- 2.7.1 SAD_MCSEG_BASE 39
- 2.7.2 SAD_MCSEG_MASK 39
- 2.7.3 SAD_MESEG_BASE 39
- 2.8 Intel QPI Link Registers 40
- 2.8.2 QPI_RMT_QPILP1_STAT_L0 41
- QPI_RMT_QPILP1_STAT_L1 41
- 2.8.3 MIP_PH_CTR_L0 41
- MIP_PH_CTR_L1 41
- 2.8.4 MIP_PH_PRT_L0 42
- MIP_PH_PRT_L1 42
- 2.9.2 MC_SMI__CNTRL 43
- 2.9.3 MC_MAX_DOD 44
- 2.9.4 MC_RD_CRDT_INIT 45
- 2.9.5 MC_SCRUBADDR_HI 46
- 2.10.1 MC_SSRCONTROL 46
- 2.10.2 MC_SCRUB_CONTROL 46
- Registers 47
- MC_CHANNEL_1_RANK_TIMING_A 48
- MC_CHANNEL_2_RANK_TIMING_A 48
- MC_CHANNEL_1_REFRESH_TIMING 50
- MC_CHANNEL_2_REFRESH_TIMING 50
- 2.12 Memory Thermal Control 53
- 2.12.5 MC_DDR_THERM1_STATUS0 55
- MC_DDR_THERM1_STATUS1 55
- MC_DDR_THERM1_STATUS2 55
- Register Description 56
- 56 Intel 56
- 3 Functional Description 57
- RAS Modes 61
- 3.5 Memory Error Signaling 62
- 3.7 2X Refresh 63
- Functional Description 64
- 64 Intel 64
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