Intel CM8064601481958 Datasheet Page 111
- Page / 125
- Table of contents
- BOOKMARKS
- Datasheet – Volume 1 of 2 1
- Contents 3
- Revision History 9
- 1.0 Introduction 10
- Supported Technologies 11
- Interfaces 12
- Power Management Support 12
- Related Documents 16
- 2.0 Interfaces 18
- System Memory Timing Support 20
- Data Scrambling 23
- 2.1.3.3 23
- PCI Express* Architecture 24
- Direct Media Interface (DMI) 26
- Processor Graphics 28
- Source Device Sink Device 33
- HDMI Source 34
- HDMI Sink 34
- PECI Bus Architecture 37
- <10pF/Node 38
- 3.0 Technologies 39
- Technology) 44
- 64 Architecture x2APIC 47
- 4.0 Power Management 49
- States Supported 50
- Enhanced Intel 51
- SpeedStep 51
- Technology Key Features 51
- Thread 0 Thread 1 52
- Core 0 State 52
- Core N State 52
- Processor Package State 52
- C1 C1E C7C6C3 53
- Core C-State Rules 54
- Package C-States 55
- DRAM I/O Power Management 63
- 4.3.2.4 63
- Graphics Power Management 64
- 5.0 Thermal Management 65
- = 0.33 * Power + 45.0 68
- Measure T 73
- (DTS) 2.0 75
- Thermal Specifications 76
- Processor Temperature 78
- Adaptive Thermal Monitor 78
- THERMTRIP# Signal 81
- Digital Thermal Sensor 81
- 5.10.1 82
- Package Power Control 83
- 5.10.2 83
- Turbo Time Parameter 84
- 5.10.3 84
- 6.0 Signal Description 86
- Testability Signals 91
- Power Sequencing Signals 92
- Table 43. Sense Signals 93
- Reserved or Unused Signals 99
- Signal Groups 99
- DC Specifications 101
- Characteristics 107
- Processor Markings 111
- Processor Land Coordinates 111
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