Intel CM8063701219000 Datasheet Page 254
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Processor Configuration Registers
254 Datasheet, Volume 2
2.18.31 VTPOLICY—DMA Remap Engine Policy Control Register
This register contains all the policy bits related to the DMA remap engine.
B/D/F/Type: 0/0/0/GFXVTBAR
Address Offset: FF0–FF3h
Reset Value: 0000_0000h
Access: RO, RO-KFW, RW-KL, RW-L
Size: 32 bits
BIOS Optimal Default 0000h
Bit Attr
Reset
Value
RST/
PWR
Description
31 RW-KL 0b Uncore
DMA Remap Engine Policy Lock-Down (DMAR_LCKDN)
This bit protects all the DMA remap engine specific policy
configuration registers. Once this bit is set by software all the DMA
remap engine registers within the range F00h to FFCh will be read
only. This bit can only be cleared through platform reset.
30:0 RO 0h Reserved
- Datasheet, Volume 2 1
- Legal Lines and Disclaimers 2
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- Revision History 10
- 1 Introduction 11
- Introduction 12
- 2 Processor Configuration 13
- 2.3 System Address Map 15
- 16 Datasheet, Volume 2 16
- HOST/SYSTEM VIEW 17
- PHYSICAL MEMORY 17
- (DRAM CONTROLLER VIEW) 17
- 2.3.1 Legacy Address Range 18
- Datasheet, Volume 2 19 19
- 2.3.2.2 TSEG 21
- 2.3.2.5 Pre-allocated Memory 22
- Datasheet, Volume 2 23 23
- 24 Datasheet, Volume 2 24
- 2.3.3.4 High BIOS Area 25
- 26 Datasheet, Volume 2 26
- Datasheet, Volume 2 27 27
- 2.3.4.3 Memory Remapping 28
- 2.3.4.5 Programming Model 28
- Datasheet, Volume 2 31 31
- 32 Datasheet, Volume 2 32
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- 2.3.11 I/O Address Space 36
- Datasheet, Volume 2 37 37
- 38 Datasheet, Volume 2 38
- Datasheet, Volume 2 39 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 44 Datasheet, Volume 2 44
- Datasheet, Volume 2 45 45
- 2.4.1 I/O Mapped Registers 46
- 2.5.6 CC—Class Code Register 53
- 2.5.30 G Memory Base Register 78
- 2.6.6 CC1—Class Code Register 90
- Register 100
- 2RW 0bUncore 102
- Port Command Register 111
- 5RW-V 0bUncore 114
- Configuration Registers 125
- 108–10Bh 126
- (16 bytes) 126
- 10C–10Dh 126
- 110–113h 127
- 23 RO 0h Reserved 127
- 114–117h 128
- 11A–11Bh 129
- 208–20Bhh 129
- 2.8.6 CC—Class Code Register 134
- Mapped Range Address Register 136
- 27 RW-L 0b 137
- 26:4 RO 000000h Uncore 137
- Device uses INTA# 139
- 2.9 Device 2 I/O Registers 142
- PCI device 145
- 2 RW 0b Uncore 161
- 5 RW-V 0b Uncore 173
- 104–107h 181
- 2.12 DMIBAR Registers 186
- 23:8 RO 0h Reserved 188
- Declaration Capability 196
- BC0–BC3h 204
- BCC–BCGh 204
- Channel 0 205
- 4294-4297h 208
- 4298-429Bh 208
- Channel 1 209
- 4694–4697h 212
- 4698–469Bh 212
- PEG/DMI/GSA streams 213
- 5004–5007h 215
- 5008–500Bh 216
- 5060–5063h 217
- Register Symbol Register Name 218
- 4CB0-4CB3h 218
- Registers 220
- 100–107h 249
- 108–10Fh 250
- 200–207h 252
- 208–20Fh 253
- FF0–FF3h 254
- 2.19 PCU MCHBAR Registers 255
- 5880–5883h 256
- 5888–588Bh 257
- Report Register 258
- Temperature Report Register 259
- Graphics Engine (GT) 260
- 5D10–5D17h 261
- 2.20 PXPEPBAR Registers 263
- 296 Datasheet, Volume 2 296
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