Intel AT80571PH0673M Datasheet download pdf (Page 31)

Datasheet 31

Electrical Specifications

2.8 Clock Specifications

2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its

default ratio during manufacturing. The processor supports Half Ratios between 7.5

and 13.5, refer to Ta b l e 16 for the processor supported ratios.

The processor uses a differential clocking implementation. For more information on the

processor clocking, contact your Intel field representative.

NOTES:

1. Individual processors operate only at or below the rated frequency.

2. Listed frequencies are not necessarily committed production frequencies.

Table 16. Core Frequency to FSB Multiplier Configuration

Multiplication of

System Core

Frequency to FSB

Frequency

Core Frequency

(266 MHz BCLK/1066 MHz

FSB)

Core Frequency

(333 MHz BCLK/

1333 MHz FSB)

Notes

1, 2

1/6

1.60 GHz

2 GHz -

1/7

1.86 GHz

2.33 GHz -

1/7.5

2 GHz

2.50 GHz -

1/8

2.13 GHz

2.66 GHz -

1/8.5

2.26 GHz

2.83 GHz -

1/9

2.40 GHz

3 GHz -

1/9.5

2.53 GHz

3.16 GHz -

1/10

2.66 GHz

3.33 GHz -

1/10.5

2.80 GHz

3.50 GHz -

1/11

2.93 GHz

3.66 GHz -

1/11.5

3.06 GHz

3.83 GHz -

1/12

3.20 GHz

4 GHz -

1/12.5

3.33 GHz

4.16 GHz -

1/13

3.46 GHz

4.33 GHz -

1/13.5

3.60GHz

4.50 GHz -

1/14

3.73 GHz

4.66 GHz -

1/15

4 GHz

5 GHz -

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 101 102

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