Intel 460GX manuals

Intel 460GX User Manual (294 pages)

Brand: Intel | Category: Motherboards | Size: 2.76 MB |

English

Table of contents

Intel® 460GX Chipset System

1

Software Developer’s Manual

1

Contents

3

Introduction 1

13

1.1.1 Component Overview

14

1.2 Product Features

15

1.4 DRAM Interface Support

16

1.5 I/O Support

16

1.6 RAS Features

17

1.8 Reference Documents

18

1.9 Revision History

19

Introduction

20

Register Descriptions 2

21

2.2 Access Restrictions

22

2.2.2 Register Attributes

23

2.2.5 Default Upon Reset

23

2.3 I/O Mapped Registers

24

2.4 Error Handling Registers

25

2.4.1.2 DEDTID: DED ITID

26

2.4.1.3 FSETID: FSE ITID

26

40h Size: 32 bits

27

44h Size: 32 bits

28

60h Size: 128 bits

29

80h Size: 8 bits

29

90h Size: 128 bits

30

2.4.2 SDC

31

68h Size: 8 bits

33

69-6Ah Size: 16 bits

33

70-77h Size: 64 bits

33

8Ch Size: 8 bits

36

CAh Size: 8 bits

38

CBh Size: 8 bits

38

D0-D7h Size: 64 bits

39

D8h Size: 8 bits

39

D9-DAh Size: 16 bits

39

E0-E7h Size: 64 bits

40

E8h Size: 8 bits

40

E9-EAh Size: 16 bits

40

: F0-F7h Size: 64 bits

40

2.4.3 MAC

41

2.4.4 PXB

42

46h Size: 8 bits

43

2.4.5 GXB

44

86h Size: 8 bits

45

8Dh Size: 8 bits

45

2.4.5.6 NERR_GART

46

2.4.6 WXB

47

45h– 46h Size: 16 bits

48

83h Size: 8 bits

48

87h Size: 8 bits

49

2.5.1 SAC

50

Config. Register

51

2.5.2 SDC

54

2.5.3 PXB

56

E8 - EBh Size: 16 bits each

57

2.5.4 GXB

58

60h Size: 64 bits

59

E0h Size: 8 bits

59

ECh, F0h Size: 32 bits

60

Monitoring Disabled

61

2.5.5 WXB

63

2.6.1 SAC

64

Register Descriptions

67

System Architecture 3

73

3.2 Ordering

74

Peer) Traffic

75

3.4 WXB Arbitration

75

3.5 Big-endian Support

76

3.6 Indivisible Operations

76

3.6.2 Inbound PCI Locks

77

3.6.3 Atomic Writes

77

3.6.4 Atomic Reads

77

3.7 Interrupt Delivery

78

3.8 WXB PCI Hot-Plug Support

78

System Architecture

80

System Address Map 4

81

System Address Map

82

4.1.5 Re-mapped Memory Areas

84

4.2 I/O Address Map

85

4G-16M to 4G-17M

87

4G-17M to 4G-18M

87

4G-18M to 4G-19M

87

4G-19M to 4G-20M

87

Memory Subsystem 5

91

5.1.1 DIMM Types

93

5.3 Bandwidth

95

5.4 Memory Subsystem Clocking

96

5.5 Supporting Features

96

5.5.3 Hardware Initialization

97

5.5.4 Memory Scrubbing

97

Memory Subsystem

98

6.1 Integrity

99

6.1.2 DRAM

100

6.1.3 Expander Buses

100

6.1.4 PCI Buses

100

6.1.5 AGP

100

6.2 Memory ECC Routing

101

6.3 Data Poisoning

101

6.4.2 BERR#/BINIT# Generation

102

6.4.3 INTREQ#

102

6.4.1 Masked Bits

102

6.5 SAC/SDC Errors

103

6.5.2 System Bus Errors

104

6.6 Error Determination

106

6.6.1 SAC Address on an Error

107

6.6.2 SDC Logging Registers

108

6.7 Clearing Errors

109

6.8 Multiple Errors

109

6.8.1 SDC Multiple Errors

110

6.8.2 SAC Multiple Errors

111

6.8.4 Error Anomalies

111

6.9 Data Flow Errors

112

6.10 Error Conditions

113

Table 6-1. Error Cases

114

6.11 PCI Integrity

118

6.11.3 PXB as Target

119

6.11.4 GXB Error Flow

120

6.11.4.1.1 GXB_XBINIT#

121

6.11.4.1.2 XINTR#

121

6.11.4.2.4 Data Errors

122

Chk parity

123

6.12.1 Integrity

124

6.12.2 Data Parity Poisoning

124

6.12.4 Error Mask Bits

125

6.12.5.1 SERR# Generation

126

6.12.6 INTRQ# Interrupt

127

6.12.8 Error Conditions

128

6.12.8.3 PCI Interface Errors

130

• System Error Signaled

130

• Discard Timer Expiration

130

AGP Subsystem 7

131

AGP Subsystem

132

7.1.1 GART Implementation

133

7.1.2 Programming GART

134

7.1.3 GART Implementation

135

7.1.4 Coherency

135

7.2 AGP Traffic

136

7.2.2 Traffic Priority

137

7.2.4 Ordering Rules

138

7.2.7 PCI Semantics Traffic

139

7.2.7.5 Inbound I/O Reads

141

7.2.7.6 Inbound Writes

141

7.2.7.7 Inbound I/O Writes

141

7.3 Bandwidth

143

7.4 Latency

144

7.5 GXB Address Map

144

WXB Hot-Plug 8

147

WXB Hot-Plug

148

00 – 01h Size: 16 bits

149

02 – 03h Size: 16 bits

149

06h – 07h Size: 16 bits

151

08h Size: 8 bits

151

8.1.7 CLASS: Class Register

152

8.1.8 CLS: Cache Line Size

152

8.1.10 HDR: Header Register

152

8.1.11 Base Address

153

8.1.13 SID: Subsystem ID

153

8.1.14 Interrupt Line

153

8.1.15 Interrupt Pin

154

8.1.18 Hot-Plug Features

155

8.1.21 Arbiter SERR Status

156

8.1.22 Memory Access Index

156

Descriptions

158

8.2.2 Slot Enable

158

8.2.3 Hot-Plug Miscellaneous

159

8.2.4 LED Control

159

8.2.6 Hot-Plug Interrupt Mask

161

8.2.7 Serial Input Byte Data

162

8.2.9 General Purpose Output

163

8.2.13 Slot Power Control

164

IFB Register Mapping 9

165

IFB Register Mapping

166

(Cont’d)

166

9.2 IDE Configuration

167

IFB Usage Considerations 10

171

10.5 Ultra DMA Configuration

172

10.5.3.1 Overview

173

10.5.6 IFB Timing Settings

179

IFB Usage Considerations

180

10.5.8 Settings Checklist

183

10.5.9 Example Configurations

184

Considerations

187

10.6 USB Resume Enable Bit

189

Registers (PCI Function 0)

191

(Function 0)

198

Address: E1h

201

Default Value: 00h

201

Attributes: Read/Write

201

Address: E8H

204

Default Value: 00112233H

204

11.2.1 DMA Registers

205

Bit Description

209

11.2.4 NMI Registers

218

Register) (I/O)

219

11.2.7 ACPI Registers

221

Address Offset: OE-0Fh

224

Default Value: 0000h

224

Size: 16 bits

224

11.2.8 SMI Registers

225

Address Offset: 1A-1Bh

226

11.2.9.1 GP Output

228

11.2.9.2 GP Data

228

11.2.9.3 GP TTL

229

11.2.9.4 GP Blink

230

11.2.9.5 GP Lock

230

11.2.9.6 GP Invert

230

11.2.9.7 GP SMI

231

11.2.9.8 GP Pulse

231

11.2.9.9 GP Core

231

11.2.9.10 GP Pull-up

231

IDE Configuration 12

233

(Function 1)

236

IDE Configuration

242

Attribute: Read/Write Clear

242

Universal Serial Bus (USB)

245

Configuration 13

245

Function 2)

246

14.2.12 Host Configuration

263

Illegal Command Field

265

Host Device Time-out

265

PCI/LPC Bridge Description 15

271

15.2.3 Modes of Operation

274

15.2.4 Cascade Mode

275

15.2.6 Interrupt Masks

276

15.2.8 Interrupt Steering

277

15.3 Serial Interrupts

278

15.3.1.4 Stop Frame

279

15.4 Timer/Counters

280

15.4.1.1 Write Operations

281

15.4.1.3 Read Operations

282

15.5 Real Time Clock

283

15.5.1 RTC Registers and RAM

284

15.5.1.1 Register A

285

15.5.1.2 Register B

286

15.5.1.3 Register C

286

15.5.2 RTC Update Cycle

287

15.5.3 RTC Interrupts

287

15.5.4 Lockable RAM Ranges

287

PCI/LPC Bridge Description

288

IFB Power Management 16

289

16.2 IFB Power Planes

290

16.2.3 SCI Generation

291

16.2.4 Sleep States

291

IFB Power Management

294

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