Intel 460GX User Manual

Intel® 460GX Chipset System Software Developer’s ManualJune 2001Document Number: 248704-001

x Intel® 460GX Chipset System Software Developer’s Manual15 PCI/LPC Bridge Description...

Data Integrity and Error Handling6-2 Intel® 460GX Chipset Software Developer’s Manual6.1.2 DRAM• The 460GX chipset provides ECC generation on all writ

Intel® 460GX Chipset Software Developer’s Manual 6-3Data Integrity and Error Handling6.2 Memory ECC RoutingThe ECC code used in DRAM is the same code

Data Integrity and Error Handling6-4 Intel® 460GX Chipset Software Developer’s ManualNote: In the SAC if there is a single-bit error and a double-bit

Intel® 460GX Chipset Software Developer’s Manual 6-5Data Integrity and Error Handling6.4.4 XBINIT#XBINIT# is an input to the SAC and an output from on

Data Integrity and Error Handling6-6 Intel® 460GX Chipset Software Developer’s Manual6.5.2 System Bus ErrorsThere are several errors that are detected

Intel® 460GX Chipset Software Developer’s Manual 6-7Data Integrity and Error HandlingThe SDC will capture the following errors on its side of the inte

Data Integrity and Error Handling6-8 Intel® 460GX Chipset Software Developer’s Manual• ‘Load’ Overlapping ‘Forward’. Set when the SDC is doing a ‘Forw

Intel® 460GX Chipset Software Developer’s Manual 6-9Data Integrity and Error HandlingOther errors capture the address associated with the failure. Thi

Data Integrity and Error Handling6-10 Intel® 460GX Chipset Software Developer’s ManualAfter this the error reporting is in the clean state. After the

Intel® 460GX Chipset Software Developer’s Manual 6-11Data Integrity and Error Handling• DEDF - first double-bit ECC error on the system bus.• PCMD - f

Intel® 460GX Chipset System Software Developer’s Manual xi7-4 GART Entry Format for 4 MB Pages...

Data Integrity and Error Handling6-12 Intel® 460GX Chipset Software Developer’s Manualcapable of any recovery. The first error, especially if it is f

Intel® 460GX Chipset Software Developer’s Manual 6-13Data Integrity and Error Handling6.8.2 SAC Multiple ErrorsThere are several important cases of mu

Data Integrity and Error Handling6-14 Intel® 460GX Chipset Software Developer’s ManualTake the case where processor 1 reads a line from memory and the

Intel® 460GX Chipset Software Developer’s Manual 6-15Data Integrity and Error Handling6.10 Error Conditions6.10.1 Table of ErrorsTable 6-1 is a list o

Data Integrity and Error Handling6-16 Intel® 460GX Chipset Software Developer’s ManualTable 6-1. Error CasesErrorChipDetectingSystemActionStatus Regis

Intel® 460GX Chipset Software Developer’s Manual 6-17Data Integrity and Error HandlingRequest Parity ErrorSAC Conditional BINIT# FERR_SAC[RQE] SA_FERR

Data Integrity and Error Handling6-18 Intel® 460GX Chipset Software Developer’s Manual‘Accept’ Underflow SDC Unconditional BINIT# SDC_FERR[AEx],FERR_

Intel® 460GX Chipset Software Developer’s Manual 6-19Data Integrity and Error HandlingGART Parity Error GXB Continue, use address as read from GART,

Data Integrity and Error Handling6-20 Intel® 460GX Chipset Software Developer’s Manual6.11 PCI IntegrityThe PCI bus provides a single even-parity bit

Intel® 460GX Chipset Software Developer’s Manual 6-21Data Integrity and Error HandlingThe default option is to return a “normal” response. If the abor

xii Intel® 460GX Chipset System Software Developer’s Manual10-10 Ultra DMA Timing Value Based on Drive Mode ...

Data Integrity and Error Handling6-22 Intel® 460GX Chipset Software Developer’s Manual• After the first data transfer if the transaction is using an u

Intel® 460GX Chipset Software Developer’s Manual 6-23Data Integrity and Error Handling6.11.4.1 GXB Error SignalsThe GXB has 2 error signals: XBINIT# a

Data Integrity and Error Handling6-24 Intel® 460GX Chipset Software Developer’s Manual6.11.4.2.2 GART Interface Errors• GART Parity Error - There is o

Intel® 460GX Chipset Software Developer’s Manual 6-25Data Integrity and Error Handling• PCI Outbound Write Que Data Parity Error - This error signifie

Data Integrity and Error Handling6-26 Intel® 460GX Chipset Software Developer’s Manual6.12 WXB Data Integrity and Error Handling6.12.1 IntegrityError

Intel® 460GX Chipset Software Developer’s Manual 6-27Data Integrity and Error HandlingNote: Additionally, error responses such as SERR#, XBINIT# and I

Data Integrity and Error Handling6-28 Intel® 460GX Chipset Software Developer’s Manual6.12.5.1 SERR# GenerationMost errors can be caused to steer the

Intel® 460GX Chipset Software Developer’s Manual 6-29Data Integrity and Error Handling6.12.5.2 XBINIT# GenerationA certain subset of errors within the

Data Integrity and Error Handling6-30 Intel® 460GX Chipset Software Developer’s Manual6.12.8 Error Conditions6.12.8.1 WXB as Bus Master6.12.8.1.1 Mast

Intel® 460GX Chipset Software Developer’s Manual 6-31Data Integrity and Error Handling(DPE) bit is asserted. Regardless, if the transaction is a read,

Intel® 460GX Chipset Software Developer’s Manual 1-1Introduction 1This document provides information about the Intel® 460GX chipset components. The 46

Data Integrity and Error Handling6-32 Intel® 460GX Chipset Software Developer’s Manual• MWI to a misaligned (non-cache-line-boundary) address• MWI to

Intel® 460GX Chipset Software Developer’s Manual 7-1AGP Subsystem 7AGP is a new port defined for graphics adapters. In the initial implementation it i

AGP Subsystem7-2 Intel® 460GX Chipset Software Developer’s Manual Figure 7-1. GART Table Usage for 4k PagesFigure 7-2. GART Table Usage for 4 MB Pa

Intel® 460GX Chipset Software Developer’s Manual 7-3AGP Subsystem7.1.1 GART ImplementationThe GX implementation will support 256 MB, 1 GB, or 32 GB (3

AGP Subsystem7-4 Intel® 460GX Chipset Software Developer’s Manual7.1.1.1 Page SizesThe Itanium processor supports both a 4kB and a 4 MB page size. The

Intel® 460GX Chipset Software Developer’s Manual 7-5AGP Subsystem7.1.3 GART ImplementationFigure 7-5 shows the timings for the SRAM interface. Synchro

AGP Subsystem7-6 Intel® 460GX Chipset Software Developer’s ManualFor all AGP-type accesses which hit in the AGP range, there is a bit per GART entry w

Intel® 460GX Chipset Software Developer’s Manual 7-7AGP SubsystemThe range may lie above the top of physical memory. Or the range may be placed in one

AGP Subsystem7-8 Intel® 460GX Chipset Software Developer’s ManualNote: Accesses from an AGP card that are directed to a PCI bus are a system fault and

Intel® 460GX Chipset Software Developer’s Manual 7-9AGP Subsystemthis point the inbound Expander logic establishes a pseudo-lock and will no-longer se

Introduction1-2 Intel® 460GX Chipset Software Developer’s Manual1.1.1 Component OverviewTable 1-1 lists the 460GX chipset components.Table 1-1. Intel®

AGP Subsystem7-10 Intel® 460GX Chipset Software Developer’s ManualDelayed transactions are issued and serviced as follows: 1. Upon receiving a read re

Intel® 460GX Chipset Software Developer’s Manual 7-11AGP Subsystem When a DRC is valid in the GXB, a 215 PCI clock timer is started as described in th

AGP Subsystem7-12 Intel® 460GX Chipset Software Developer’s Manual7.2.7.8 Retry/Disconnect ConditionsThe GXB as a PCI target retries the initial data

Intel® 460GX Chipset Software Developer’s Manual 7-13AGP Subsystem7.2.7.11 Fast Back-to-Back TransactionsThe GXB as a PCI target will accept fast back

AGP Subsystem7-14 Intel® 460GX Chipset Software Developer’s Manual7.3.1 Inbound Read PrefetchingThe PCI protocol has no transfer size explicitly spell

Intel® 460GX Chipset Software Developer’s Manual 7-15AGP SubsystemAll regions, including the two described above, must be checked after GART translati

AGP Subsystem7-16 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 8-1WXB Hot-Plug 88.1 IHPC Configuration RegistersEach WXB supports two independent Integrated Hot-Pl

WXB Hot-Plug8-2 Intel® 460GX Chipset Software Developer’s ManualTable 8-1. IHPC Configuration Register SpaceDID VID00h 80hPCISTS PCICMD04h 84hCLASS RI

Intel® 460GX Chipset Software Developer’s Manual 8-3WXB Hot-Plug8.1.1 Page Number List for the IHPC PCI Register DescriptionsRegister PageArbiter SERR

Intel® 460GX Chipset Software Developer’s Manual 1-3Introduction1.2 Product Features1.3 Itanium™ Processor System Bus Support• Full support for the It

WXB Hot-Plug8-4 Intel® 460GX Chipset Software Developer’s Manual8.1.4 PCICMD: PCI Command RegisterAddress Offset: 04h-05h Size: 16 bits Default Value:

Intel® 460GX Chipset Software Developer’s Manual 8-5WXB Hot-Plug8.1.5 PCISTS: PCI Status RegisterAddress Offset: 06h – 07h Size: 16 bits Default Value

WXB Hot-Plug8-6 Intel® 460GX Chipset Software Developer’s ManualBits Description7:0 Revision Identification NumberThis is an 8-bit value that indicate

Intel® 460GX Chipset Software Developer’s Manual 8-7WXB Hot-PlugBits Description7 Multi-function DeviceSelects whether this is a multi-function device

WXB Hot-Plug8-8 Intel® 460GX Chipset Software Developer’s ManualThis is a standard PCI configuration register which defines which interrupt request li

Intel® 460GX Chipset Software Developer’s Manual 8-9WXB Hot-Plug11:8 reserved(0)7 Enable PCI Configuration Space Access to Hot-Plug Registers. Enables

WXB Hot-Plug8-10 Intel® 460GX Chipset Software Developer’s Manual8.1.21 Arbiter SERR StatusAddress Offset: 4A Size: 8 bitsDefault Value: 00h Attribut

Intel® 460GX Chipset Software Developer’s Manual 8-11WXB Hot-PlugTable 8-2. IHPC Memor Mapped Register SpaceHot-Plug Miscellaneous (RW)Slot Enable (RW

WXB Hot-Plug8-12 Intel® 460GX Chipset Software Developer’s Manual8.2.1 Page Number List for IHPC Memory Mapped Register DescriptionsRegister PageExten

Intel® 460GX Chipset Software Developer’s Manual 8-13WXB Hot-Plug8.2.3 Hot-Plug MiscellaneousAddress Offset: 02h - 03h Size: 16 bitsDefault Value: 004

Introduction1-4 Intel® 460GX Chipset Software Developer’s Manual1.4 DRAM Interface Support• SDRAM 3.3 volt, 168-pin DIMM’s are the only memory type su

WXB Hot-Plug8-14 Intel® 460GX Chipset Software Developer’s Manualfor unpopulated slots and slots with open switches. The set of usable LED Control bit

Intel® 460GX Chipset Software Developer’s Manual 8-15WXB Hot-Pluginto this register. Writing a logic 1 will clear the pending interrupt. If there are

WXB Hot-Plug8-16 Intel® 460GX Chipset Software Developer’s ManualBits Description31:30 reserved (0)29 Slot F PRSNT(0)#, PCI Present Signal 128 Slot E

Intel® 460GX Chipset Software Developer’s Manual 8-17WXB Hot-Plug8.2.8 Serial Input Byte PointerAddress Offset: 11h Size: 16 bitsDefault Value: 00h A

WXB Hot-Plug8-18 Intel® 460GX Chipset Software Developer’s Manual8.2.12 Hot-Plug Switch Interrupt Redirect EnableAddress Offset: 2Ch Size: 8 bits Defa

Intel® 460GX Chipset Software Developer’s Manual 9-1IFB Register Mapping 9The IFB internal registers are organized into four Functions–LPC/FWH interfa

IFB Register Mapping9-2 Intel® 460GX Chipset Software Developer’s Manual06–07h PCISTS PCI Device Status R/W08h RID Revision Identification RO09-0Bh CL

Intel® 460GX Chipset Software Developer’s Manual 9-3IFB Register Mapping9.2 IDE ConfigurationThe IFB PCI function 1 contains an IDE Controller capable

IFB Register Mapping9-4 Intel® 460GX Chipset Software Developer’s Manual9.3 Universal Serial Bus (USB) ConfigurationThe IFB integrates an USB Controll

Intel® 460GX Chipset Software Developer’s Manual 9-5IFB Register Mapping9.4 SMBus Controller ConfigurationThe IFB PCI function 3 contains the SMBus Co

Intel® 460GX Chipset Software Developer’s Manual 1-5Introduction• Parity protection on all PCI signals. • Data collection & write assembly. — Comb

IFB Register Mapping9-6 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 10-1IFB Usage Considerations 10This section talks about the normal usage for some of the features in

IFB Usage Considerations10-2 Intel® 460GX Chipset Software Developer’s Manualinto the system firmware by the vendor. This reporting will make these re

Intel® 460GX Chipset Software Developer’s Manual 10-3IFB Usage ConsiderationsNOTES:• The Ultra DMA Enable bit specifies the current Ultra DMA enabled

IFB Usage Considerations10-4 Intel® 460GX Chipset Software Developer’s ManualFor IFB IDE Timing Configuration, each of the following things must be de

Intel® 460GX Chipset Software Developer’s Manual 10-5IFB Usage Considerations10.5.4 Determining a Drive’s Best Ultra DMA CapabilityThe drive’s ultra D

IFB Usage Considerations10-6 Intel® 460GX Chipset Software Developer’s ManualThe drive’s multi word DMA mode capability and current configuration are

Intel® 460GX Chipset Software Developer’s Manual 10-7IFB Usage ConsiderationsNOTE: Timing cycle times are defined by the ATA specification. A device t

IFB Usage Considerations10-8 Intel® 460GX Chipset Software Developer’s ManualSoftware at this stage needs to determine if at least one of the above mo

Intel® 460GX Chipset Software Developer’s Manual 10-9IFB Usage Considerations10.5.6 IFB Timing Settings10.5.6.1 DMA/PIO Timing SettingsIn Table 10-7,

Introduction1-6 Intel® 460GX Chipset Software Developer’s Manual• I2C Slave Interface will allow viewing and modifying of specific error and configura

IFB Usage Considerations10-10 Intel® 460GX Chipset Software Developer’s ManualConfigurations where a drive reports a PIO speed much slower than its re

Intel® 460GX Chipset Software Developer’s Manual 10-11IFB Usage Considerations10.5.6.2 Ultra DMA Timing SettingsThe following settings apply to Ultra

IFB Usage Considerations10-12 Intel® 460GX Chipset Software Developer’s ManualRefer to the Set Features Command description in the ATA Specification f

Intel® 460GX Chipset Software Developer’s Manual 10-13IFB Usage Considerations10.5.7.1 BMIS1 - Bus Master IDE Status Register 1(Primary: Bus Master ID

IFB Usage Considerations10-14 Intel® 460GX Chipset Software Developer’s Manual10.5.9 Example ConfigurationsThis section provides examples of drive con

Intel® 460GX Chipset Software Developer’s Manual 10-15IFB Usage Considerations10.5.9.2 Example #2: Mixed Ultra DMA/33 and Non-ultra DMA/33 Configurati

IFB Usage Considerations10-16 Intel® 460GX Chipset Software Developer’s ManualIn the above configuration, none of the drives supports Ultra DMA. Only

Intel® 460GX Chipset Software Developer’s Manual 10-17IFB Usage ConsiderationsII. Provide recovery for data transfers that fail as the result of Ultra

IFB Usage Considerations10-18 Intel® 460GX Chipset Software Developer’s ManualThis register enables/disables bus master capability for the IDE functio

Intel® 460GX Chipset Software Developer’s Manual 10-19IFB Usage Considerations10.6 USB Resume Enable BitTwo bits have been added to the USB Host contr

Intel® 460GX Chipset Software Developer’s Manual 1-7Introduction• JTAG IEEE 1149.1 Specification (http://www.ieee.com)• Universal Serial Bus Specifica

IFB Usage Considerations10-20 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 11-1LPC/FWH Interface Configuration 11The IFB PCI Function 0 contains a LPC/FWH interface, interrupt

LPC/FWH Interface Configuration11-2 Intel® 460GX Chipset Software Developer’s Manual11.1.3 PCICMD–PCI Command Register (Function 0)Address Offset: 04–

Intel® 460GX Chipset Software Developer’s Manual 11-3LPC/FWH Interface Configuration11.1.5 RID–Revision Identification Register (Function 0)Address Of

LPC/FWH Interface Configuration11-4 Intel® 460GX Chipset Software Developer’s Manual11.1.8 ACPI Base Address (Function 0)Address: 40-43hDefault Value:

Intel® 460GX Chipset Software Developer’s Manual 11-5LPC/FWH Interface Configuration11.1.11 BIOSEN–BIOS Enable Register (FUNCTION 0)Address Offset: 4E

LPC/FWH Interface Configuration11-6 Intel® 460GX Chipset Software Developer’s Manual11.1.13 SerIRQC–Serial IRQ Control Register (Function 0)Address Of

Intel® 460GX Chipset Software Developer’s Manual 11-7LPC/FWH Interface Configuration11.1.15 MSTAT–Miscellaneous Status Register (Function 0)Address Of

LPC/FWH Interface Configuration11-8 Intel® 460GX Chipset Software Developer’s Manual11.1.17 MGPIOC–Muxed GPIO Control (Function 0)Offset: 84-85hDefaul

Intel® 460GX Chipset Software Developer’s Manual 11-9LPC/FWH Interface ConfigurationThese registers provide the base address for distributed DMA slave

ii Intel® 460GX Chipset System Software Developer’s ManualTHIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF M

Introduction1-8 Intel® 460GX Chipset Software Developer’s Manual

LPC/FWH Interface Configuration11-10 Intel® 460GX Chipset Software Developer’s Manual11.1.21 GPIO Base Address (FUNCTION 0)Address: D0-D3hDefault Valu

Intel® 460GX Chipset Software Developer’s Manual 11-11LPC/FWH Interface Configuration11.1.24 LPC FDD/LPT Decode Ranges (Function 0)Address: E1hDefault

LPC/FWH Interface Configuration11-12 Intel® 460GX Chipset Software Developer’s Manual11.1.25 LPC Sound Decode Ranges (Function 0)Address: E2hDefault V

Intel® 460GX Chipset Software Developer’s Manual 11-13LPC/FWH Interface Configuration11.1.27 LPC Enables (Function 0)Address: E6-E7hDefault Value: 000

LPC/FWH Interface Configuration11-14 Intel® 460GX Chipset Software Developer’s Manual11.1.27.2 Firmware Hub (FWH) Select Register Address: E8HDefault

Intel® 460GX Chipset Software Developer’s Manual 11-15LPC/FWH Interface Configuration11.1.27.3 Test Mode RegisterAddress: FC-FFhDefault Value: 0000000

LPC/FWH Interface Configuration11-16 Intel® 460GX Chipset Software Developer’s Manual11.2.1.2 Dcm–Dma Channel Mode Register (I/O)I/O Address: Channels

Intel® 460GX Chipset Software Developer’s Manual 11-17LPC/FWH Interface Configuration11.2.1.4 WSMB–Write Single Mask Bit (I/O)I/O Address: Channels 0-

LPC/FWH Interface Configuration11-18 Intel® 460GX Chipset Software Developer’s Manual11.2.1.6 Ds–Dma Status Register (I/O)I/O Address: Channels 0-3–08

Intel® 460GX Chipset Software Developer’s Manual 11-19LPC/FWH Interface Configuration11.2.1.8 DBCNT–Dma Base and Current Count Registers (I/O)I/O Addr

Intel® 460GX Chipset Software Developer’s Manual 2-1Register Descriptions 2The 460GX chipset has both memory mapped and PCI configuration space mapped

LPC/FWH Interface Configuration11-20 Intel® 460GX Chipset Software Developer’s Manual11.2.1.11 Dmc–Dma Master Clear Register (I/O)I/O Address: Channel

Intel® 460GX Chipset Software Developer’s Manual 11-21LPC/FWH Interface Configuration11.2.2.2 Icw2–Initialization Command Word 2 Register (I/O)I/O Add

LPC/FWH Interface Configuration11-22 Intel® 460GX Chipset Software Developer’s Manual11.2.2.4 Icw3–Initialization Command Word 3 Register (I/O)I/O Add

Intel® 460GX Chipset Software Developer’s Manual 11-23LPC/FWH Interface Configuration11.2.2.7 Ocw2–Operational Control Word 2 Register (I/O)I/O Addres

LPC/FWH Interface Configuration11-24 Intel® 460GX Chipset Software Developer’s Manual11.2.2.9 Elcr1–Edge/Level Control Register (I/O)I/O Address: INT

Intel® 460GX Chipset Software Developer’s Manual 11-25LPC/FWH Interface Configuration11.2.2.10 Elcr2–Edge/Level Control Register (I/O)I/O Address: INT

LPC/FWH Interface Configuration11-26 Intel® 460GX Chipset Software Developer’s ManualThe Timer Control Word Register specifies the counter selection,

Intel® 460GX Chipset Software Developer’s Manual 11-27LPC/FWH Interface ConfigurationRegister bit definitions are different during the Counter Latch C

LPC/FWH Interface Configuration11-28 Intel® 460GX Chipset Software Developer’s Manual11.2.4 NMI RegistersThe NMI logic incorporates two different 8-bi

Intel® 460GX Chipset Software Developer’s Manual 11-29LPC/FWH Interface Configuration11.2.4.2 NmiEN–Nmi Enable Register (Shared with Real-time Clock I

Register Descriptions2-2 Intel® 460GX Chipset Software Developer’s Manualto a PCI bus. Reads result in data being returned by the xXB through the SAC

LPC/FWH Interface Configuration11-30 Intel® 460GX Chipset Software Developer’s Manual11.2.5.3 RTCEI–Real-time Clock Extended Index Register (I/O)I/O A

Intel® 460GX Chipset Software Developer’s Manual 11-31LPC/FWH Interface Configuration11.2.6.2 APMS–Advanced Power Management Status Port (I/O)I/O Addr

LPC/FWH Interface Configuration11-32 Intel® 460GX Chipset Software Developer’s Manual11.2.7.2 Power Management 1 EnableAddress Offset: 02-03hAttribute

Intel® 460GX Chipset Software Developer’s Manual 11-33LPC/FWH Interface Configuration11.2.7.4 Power Management 1 TimerAddress Offset: 08-0BhAttributes

LPC/FWH Interface Configuration11-34 Intel® 460GX Chipset Software Developer’s Manual11.2.7.6 General Purpose 0 EnableAddress Offset: OE-0FhAttributes

Intel® 460GX Chipset Software Developer’s Manual 11-35LPC/FWH Interface Configuration11.2.7.7 General Purpose 1 StatusAddress Offset: 16-17hAttributes

LPC/FWH Interface Configuration11-36 Intel® 460GX Chipset Software Developer’s Manual11.2.8.1 Global Control and EnableAddress Offset: 1A-1BhAttribute

Intel® 460GX Chipset Software Developer’s Manual 11-37LPC/FWH Interface Configuration11.2.8.2 Global Status RegisterAddress Offset: 1Ch-1Dh Attributes

LPC/FWH Interface Configuration11-38 Intel® 460GX Chipset Software Developer’s Manual11.2.9.1 GP OutputOffset: 00-03hAttribute: Read/WriteDefault Valu

Intel® 460GX Chipset Software Developer’s Manual 11-39LPC/FWH Interface Configuration11.2.9.3 GP TTLOffset: 08-0BhAttribute: Read/WriteDefault Value:

Intel® 460GX Chipset Software Developer’s Manual 2-3Register Descriptionstranslates CF8/CFC accesses to the MAC registers into read/write commands ove

LPC/FWH Interface Configuration11-40 Intel® 460GX Chipset Software Developer’s Manual11.2.9.4 GP BlinkOffset: 0C-0FhAttribute: Read/WriteDefault Value

Intel® 460GX Chipset Software Developer’s Manual 11-41LPC/FWH Interface Configuration11.2.9.7 GP SMIOffset: 1C-1FhAttribute: Read/WriteDefault Value:

LPC/FWH Interface Configuration11-42 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 12-1IDE Configuration 12The IFB PCI Function 1 contains an IDE Controller capable of Programmed I/O (

IDE Configuration12-2 Intel® 460GX Chipset Software Developer’s Manual12.2.1 VID–Vendor Identification Register (Function 1)Address Offset: 00–01hDefa

Intel® 460GX Chipset Software Developer’s Manual 12-3IDE Configuration12.2.4 PCISTS–PCI Device Status Register (Function 1)Address Offset: 06–07hDefau

IDE Configuration12-4 Intel® 460GX Chipset Software Developer’s Manual12.2.6 MLT–Master Latency Timer Register (Function 1)Address Offset: 0DhDefault

Intel® 460GX Chipset Software Developer’s Manual 12-5IDE Configuration12.2.8 SVID–Subsystem Vendor ID (Function 1)Address: 2C-2DhDefault Value: 0000hA

IDE Configuration12-6 Intel® 460GX Chipset Software Developer’s Manual12.2.11 SIDETIM–Slave IDE Timing Register (Function 1)Address Offset: 44hDefault

Intel® 460GX Chipset Software Developer’s Manual 12-7IDE Configuration12.2.12 DMACTL–Synchronous DMA Control Register (Function 1)Address Offset: 48hD

Register Descriptions2-4 Intel® 460GX Chipset Software Developer’s Manual2.2.6 ConsistencyThere are a number of registers that are repeated in both th

IDE Configuration12-8 Intel® 460GX Chipset Software Developer’s Manual12.2.13 SDMATIM–Synchronous DMA Timing Register (Function 1)Address Offset: 4A-4

Intel® 460GX Chipset Software Developer’s Manual 12-9IDE ConfigurationNOTES:1. Table 12-3 assumes that if the attached slave drive is Mode 0 or not pr

IDE Configuration12-10 Intel® 460GX Chipset Software Developer’s Manual12.3.2 BMISx–Bus Master IDE Status Register (I/O)Address Offset: Primary Channe

Intel® 460GX Chipset Software Developer’s Manual 12-11IDE Configuration12.3.3 BMIDTPx–Bus Master IDE Descriptor Table Pointer Register (I/O)Address Of

IDE Configuration12-12 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 13-1Universal Serial Bus (USB) Configuration 13The IFB integrates one USB Controller. The USB Control

Universal Serial Bus (USB) Configuration13-2 Intel® 460GX Chipset Software Developer’s Manual13.2 USB Host Controller Register Descriptions (PCI Funct

Intel® 460GX Chipset Software Developer’s Manual 13-3Universal Serial Bus (USB) Configuration13.2.4 PCISTS–PCI Device Status Register (Function 2)Addr

Universal Serial Bus (USB) Configuration13-4 Intel® 460GX Chipset Software Developer’s Manual13.2.6 CLASSC–Class Code Register (Function 2)Address Off

Intel® 460GX Chipset Software Developer’s Manual 13-5Universal Serial Bus (USB) Configuration13.2.9 USBBA–USB I/O Space Base Address (Function 2)Addre

Intel® 460GX Chipset Software Developer’s Manual 2-5Register Descriptionssubordinate bus number is in that range. For a type 1 cycle, the Bus Number i

Universal Serial Bus (USB) Configuration13-6 Intel® 460GX Chipset Software Developer’s Manual13.2.13 INTPN–Interrupt Pin (Function 2)Address Offset: 3

Intel® 460GX Chipset Software Developer’s Manual 13-7Universal Serial Bus (USB) ConfigurationBit Description15 End OF A20GATE Pass Through Status (A20

Universal Serial Bus (USB) Configuration13-8 Intel® 460GX Chipset Software Developer’s Manual13.2.17 USBREN–USB Resume EnableAddress Offset: C4hDefaul

Intel® 460GX Chipset Software Developer’s Manual 13-9Universal Serial Bus (USB) Configuration3 Enter Global Suspend Mode (EGSM). 1=Host Controller ent

Universal Serial Bus (USB) Configuration13-10 Intel® 460GX Chipset Software Developer’s Manual13.3.2 USBSTS–USB Status Register (I/O)I/O Address: Base

Intel® 460GX Chipset Software Developer’s Manual 13-11Universal Serial Bus (USB) Configuration13.3.4 FRNUM–Frame Number Register (I/O)I/O Address: Bas

Universal Serial Bus (USB) Configuration13-12 Intel® 460GX Chipset Software Developer’s Manualrequired by the USB specification. It’s initial programm

Intel® 460GX Chipset Software Developer’s Manual 13-13Universal Serial Bus (USB) Configuration12 Suspend–R/W. 1=Port in suspend state. 0=Port not in s

Universal Serial Bus (USB) Configuration13-14 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 14-1SM Bus Controller Configuration 14The IFB PCI Function 3 contains the SMBus Controller configurat

Register Descriptions2-6 Intel® 460GX Chipset Software Developer’s ManualBits Description7 Disable This bit can be written by software. When set, the

SM Bus Controller Configuration14-2 Intel® 460GX Chipset Software Developer’s Manual14.2 System Management Register DescriptionsThis section describes

Intel® 460GX Chipset Software Developer’s Manual 14-3SM Bus Controller Configuration14.2.4 PCISTS–PCI Device Status Register (Function 3)Address Offse

SM Bus Controller Configuration14-4 Intel® 460GX Chipset Software Developer’s Manual14.2.6 CLASSC–Class Code Register (Function 3)Address Offset: 09-0

Intel® 460GX Chipset Software Developer’s Manual 14-5SM Bus Controller Configuration14.2.9 SID–Subsystem ID (Function 3)Address: 2E-2FhDefault Value:

SM Bus Controller Configuration14-6 Intel® 460GX Chipset Software Developer’s Manual14.2.13 smbslvc–SMBus Slave Command (Function 3)Address Offset: 41

Intel® 460GX Chipset Software Developer’s Manual 14-7SM Bus Controller Configuration14.3.1 smbhststs–SMBus Host Status Register (I/O)I/O Address: Base

SM Bus Controller Configuration14-8 Intel® 460GX Chipset Software Developer’s Manual14.3.3 smbhstcnt–SMBus Host Control Register (I/O)I/O Address: Bas

Intel® 460GX Chipset Software Developer’s Manual 14-9SM Bus Controller Configuration14.3.4 smbhstcmd–SMBus Host Command Register (I/O)I/O Address: Bas

SM Bus Controller Configuration14-10 Intel® 460GX Chipset Software Developer’s Manual14.3.7 smbhstdat1–SMBus Host Data 1 Register (I/O)I/O Address: Ba

Intel® 460GX Chipset Software Developer’s Manual 14-11SM Bus Controller Configuration14.3.9.1 10.3.10.smbshdwcmd–SMBus Shadow Command Register (I/O)I/

Intel® 460GX Chipset Software Developer’s Manual 2-7Register DescriptionsBits Description7 Disable This bit can be written by software. When set, the

SM Bus Controller Configuration14-12 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 15-1PCI/LPC Bridge Description 1515.1 PCI Interface The IFB incorporates a fully PCI Bus compatible m

PCI/LPC Bridge Description15-2 Intel® 460GX Chipset Software Developer’s Manualinternal interrupts are used for internal Functions only. IRQ2 is used

Intel® 460GX Chipset Software Developer’s Manual 15-3PCI/LPC Bridge DescriptionFor CNTRL-2, ICW3 is the slave identification code used during an inter

PCI/LPC Bridge Description15-4 Intel® 460GX Chipset Software Developer’s Manualperform a non-specific EOI operation at the trailing edge of the last i

Intel® 460GX Chipset Software Developer’s Manual 15-5PCI/LPC Bridge Description15.2.3.4 Specific Rotation (Specific Priority) The programmer can chang

PCI/LPC Bridge Description15-6 Intel® 460GX Chipset Software Developer’s Manual15.2.5 Edge and Level Triggered Mode This mode is programmed using bit

Intel® 460GX Chipset Software Developer’s Manual 15-7PCI/LPC Bridge DescriptionThus, any interrupts may be selectively enabled by loading the Mask Reg

PCI/LPC Bridge Description15-8 Intel® 460GX Chipset Software Developer’s Manualindividual PIRQx# line to any one of 11 IRQ inputs. The assignment is p

Intel® 460GX Chipset Software Developer’s Manual 15-9PCI/LPC Bridge DescriptionDuring the Sample phase, the device drives SERIRQ low if the correspond

Register Descriptions2-8 Intel® 460GX Chipset Software Developer’s Manual18 ‘Completion’ Command Underflow; MAC B, Stack R (CCBR)One of these 4 bits i

PCI/LPC Bridge Description15-10 Intel® 460GX Chipset Software Developer’s Manual15.4 Timer/CountersThe IFB contains three counters that are equivalent

Intel® 460GX Chipset Software Developer’s Manual 15-11PCI/LPC Bridge DescriptionThe Counter Latch Command latches the current count so that it can be

PCI/LPC Bridge Description15-12 Intel® 460GX Chipset Software Developer’s ManualIf a counter is programmed to read/write two-byte counts, the followin

Intel® 460GX Chipset Software Developer’s Manual 15-13PCI/LPC Bridge DescriptionIf a counter is programmed to read/write two-byte counts, a program mu

PCI/LPC Bridge Description15-14 Intel® 460GX Chipset Software Developer’s ManualThe time and calendar data should match the data mode (BCD or binary)

Intel® 460GX Chipset Software Developer’s Manual 15-15PCI/LPC Bridge DescriptionThe extended RAM bank is also accessed using an indexed scheme. I/O ad

PCI/LPC Bridge Description15-16 Intel® 460GX Chipset Software Developer’s Manual15.5.1.2 Register BAddress Offset: 0BhDefault Value: X0000XXXbAttribut

Intel® 460GX Chipset Software Developer’s Manual 15-17PCI/LPC Bridge Description15.5.1.4 Register DAddress Offset: 0DhDefault Value: NA - This registe

PCI/LPC Bridge Description15-18 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 16-1IFB Power Management 1616.1 OverviewIFB is designed for desktop systems, and includes the follow

Intel® 460GX Chipset Software Developer’s Manual 2-9Register Descriptions2.4.1.6 SA_FERR: System Address on First Error Bus CBN, Device Number: 00h Fu

IFB Power Management16-2 Intel® 460GX Chipset Software Developer’s Manual16.2 IFB Power Planes16.2.1 Power Plane DescriptionsThe IFB contains three po

Intel® 460GX Chipset Software Developer’s Manual 16-3IFB Power Management16.2.3 SCI GenerationIn an ACPI environment, an SCI (system control interrupt

IFB Power Management16-4 Intel® 460GX Chipset Software Developer’s Manual16.2.5 ACPI Bits Not Implemented by IFBMany ACPI registers and bits are optio

Intel® 460GX Chipset Software Developer’s Manual 16-5IFB Power ManagementA Wake event will cause an exit from the Soft-Off state. The wake events that

IFB Power Management16-6 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset System Software Developer’s Manual iiiContents1 Introduction...

Register Descriptions2-10 Intel® 460GX Chipset Software Developer’s Manual2.4.1.8 BIUDATA: BIU Data Register Bus CBN, Device Number: 00h Function: 1Ad

Intel® 460GX Chipset Software Developer’s Manual 2-11Register Descriptions2.4.2 SDC2.4.2.1 SEC0_D_FERR: Data on First Memory Card B SECBus CBN, Device

Register Descriptions2-12 Intel® 460GX Chipset Software Developer’s Manual2.4.2.4 DED0_D_FERR: Data on First Memory Card B DEDBus CBN, Device Number:

Intel® 460GX Chipset Software Developer’s Manual 2-13Register DescriptionsThis register records and latches the data corresponding to the first SEC de

Register Descriptions2-14 Intel® 460GX Chipset Software Developer’s Manual2.4.2.11 DED1_ECC_FERR: ECC on First Memory Card A DEDBus CBN, Device Number

Intel® 460GX Chipset Software Developer’s Manual 2-15Register Descriptions26 ’Forward’ Overlapping ’Forward’; Card A (FWMDI1)Indicates FWMDI sampled a

Register Descriptions2-16 Intel® 460GX Chipset Software Developer’s Manual5 System Bus Double Bit Error (DEDF)ECC Double Bit Error Detected on system

Intel® 460GX Chipset Software Developer’s Manual 2-17Register DescriptionsThis register records and latches the data associated with the first parity

Register Descriptions2-18 Intel® 460GX Chipset Software Developer’s Manualwhile masked will return an invalid ECC code. To disable testing, the mask v

Intel® 460GX Chipset Software Developer’s Manual 2-19Register Descriptions5 Memory Bus A ECC correction/detection enable.4 Memory Bus B ECC correction

iv Intel® 460GX Chipset System Software Developer’s Manual3 System Architecture...

Register Descriptions2-20 Intel® 460GX Chipset Software Developer’s Manual2.4.2.26 SECF_D_FERR: Data on First System Bus SECBus CBN, Device Number: 04

Intel® 460GX Chipset Software Developer’s Manual 2-21Register DescriptionsThis register records and latches the data corresponding to the first DED de

Register Descriptions2-22 Intel® 460GX Chipset Software Developer’s Manual0 Parity Error - CMND Parity Error Detected on SAC-MAC CMND Bus. Look in CMN

Intel® 460GX Chipset Software Developer’s Manual 2-23Register Descriptions3 Inbound Delayed Read Time-out FlagEach inbound read request that is accept

Register Descriptions2-24 Intel® 460GX Chipset Software Developer’s Manual2.4.5 GXB2.4.5.1 FERR_GXBFunction Number: BFN+1Address Offset: 80h Size: 8 b

Intel® 460GX Chipset Software Developer’s Manual 2-25Register DescriptionsDefault Value: 00h Attribute: Read/Write ClearSticky: Yes Locked: NoThese re

Register Descriptions2-26 Intel® 460GX Chipset Software Developer’s Manual2.4.5.6 NERR_GARTFunction Number: BFN+1Address Offset: 8Eh Size: 8 bitsDefau

Intel® 460GX Chipset Software Developer’s Manual 2-27Register Descriptions2.4.6 WXB2.4.6.1 ERRSTS: Error Status RegisterAddress Offset: 44h Size: 8 bi

Register Descriptions2-28 Intel® 460GX Chipset Software Developer’s Manual2.4.6.2 ERRCMD: Error Command RegisterAddress Offset: 45h– 46h Size: 16 bits

Intel® 460GX Chipset Software Developer’s Manual 2-29Register Descriptionseach of these errors varies and is (generally) controlled through a combinat

Intel® 460GX Chipset System Software Developer’s Manual v6.1.6 Private Bus between SAC and SDC ...6-

Register Descriptions2-30 Intel® 460GX Chipset Software Developer’s Manual2.4.6.5 FEPCIAL: PCI First Error Address/Command LogAddress Offset: A5h–ADh

Intel® 460GX Chipset Software Developer’s Manual 2-31Register DescriptionsThe IT_MON_PMD_[0 to 5] registers hold the performance monitoring count valu

Register Descriptions2-32 Intel® 460GX Chipset Software Developer’s Manual23:15 UMASK Encodings0 0000 0000 - Processor 0 - Monitor transactions origin

Intel® 460GX Chipset Software Developer’s Manual 2-33Register Descriptions001 0111b Memory Read that was to be retried and received a HITM001 1000b Me

Register Descriptions2-34 Intel® 460GX Chipset Software Developer’s Manual2.5.2 SDC2.5.2.1 FSB_D_PMC_[1,0]: System Bus Performance Monitor Configurati

Intel® 460GX Chipset Software Developer’s Manual 2-35Register Descriptions01b Disable when counter overflows.10b Disable on falling edge (Deassertion)

Register Descriptions2-36 Intel® 460GX Chipset Software Developer’s Manual2.5.3 PXB2.5.3.1 PMD[1:0]: Performance Monitoring Data RegisterAddress Offse

Intel® 460GX Chipset Software Developer’s Manual 2-37Register DescriptionsOnce configured to count, all counters in the SAC and each PXB can be (nearl

Register Descriptions2-38 Intel® 460GX Chipset Software Developer’s Manual5:0 Event Selection This field specifies the basic PCI bus transaction or PC

Intel® 460GX Chipset Software Developer’s Manual 2-39Register Descriptions38:0 Count ValueThis register contains the Performance Monitor Data Register

vi Intel® 460GX Chipset System Software Developer’s Manual7.2 AGP Traffic...

Register Descriptions2-40 Intel® 460GX Chipset Software Developer’s Manual0 Event 0 InputThis bit is fed an input into Event 0 logic. This bit is OR’

Intel® 460GX Chipset Software Developer’s Manual 2-41Register Descriptions7 EVENT1 Count EnableIf set, then this bit over-rides bits 13:8. If set, the

Register Descriptions2-42 Intel® 460GX Chipset Software Developer’s Manual00 0010b All PCI Clocks00 0100b Idle Bus Cycles00 0111b All Disconnect Event

Intel® 460GX Chipset Software Developer’s Manual 2-43Register Descriptions2.5.5 WXB2.5.5.1 PCI_WXB_PMC0: PCI Performance Monitor Configuration Registe

Register Descriptions2-44 Intel® 460GX Chipset Software Developer’s Manual2.5.5.2 PCI_WXB_PMC1: PCI Performance Monitor Configuration RegisterAddress

Intel® 460GX Chipset Software Developer’s Manual 2-45Register Descriptions15:8 XTPR 1These bits represent the external task priority for symmetric age

Register Descriptions2-46 Intel® 460GX Chipset Software Developer’s Manual2.6.2.2 I/O Window Register (FEC00010h)This register is mapped onto the PID’

Intel® 460GX Chipset Software Developer’s Manual 2-47Register Descriptions2.6.3.1 I/O (x)APIC ID Register (00h)Table 2-6. Memory-mapped Register Summa

Register Descriptions2-48 Intel® 460GX Chipset Software Developer’s ManualThe I/O (x)APIC ID register is read/write by software. On reset, this regist

Intel® 460GX Chipset Software Developer’s Manual 2-49Register Descriptions2.6.3.2 I/O (x)APIC Version Register (01h)The PID contains an I/O (x)APIC ve

Intel® 460GX Chipset System Software Developer’s Manual vii8.2.14 Extended Hot-Plug Miscellaneous ...

Register Descriptions2-50 Intel® 460GX Chipset Software Developer’s Manual2.6.3.4 I/O (x)APIC RTE (10h-8Fh)The interrupt RT has a dedicated entry for

Intel® 460GX Chipset Software Developer’s Manual 2-51Register Descriptions16 MASK MASK This bit masks the (x)APIC delivery of this interrupt.A 0 indic

Register Descriptions2-52 Intel® 460GX Chipset Software Developer’s Manual11 DESTINATION MODEDESTINATION MODEThis bit determines the interpretation of

Intel® 460GX Chipset Software Developer’s Manual 3-1System Architecture 3This chapter provides an explanation of the 460GX chipset’s handling of vario

System Architecture3-2 Intel® 460GX Chipset Software Developer’s ManualFor WC memory, one processor may write to an address that is marked WC in its p

Intel® 460GX Chipset Software Developer’s Manual 3-3System ArchitectureNew EM code may be weakly ordered. To allow the processor to take advantage of

System Architecture3-4 Intel® 460GX Chipset Software Developer’s ManualArbitration for Outbound TransactionsThe WXB relies heavily on the PCIset core

Intel® 460GX Chipset Software Developer’s Manual 3-5System ArchitectureAGP LOCKSThere is no LOCK signal on the AGP bus. However, legacy code that issu

System Architecture3-6 Intel® 460GX Chipset Software Developer’s Manuallocation, there is no guarantee that AGP has not written the location while the

Intel® 460GX Chipset Software Developer’s Manual 3-7System Architecture3.8.1 Slot Power-up and EnableTo power-up a PCI slot, software sets a command b

viii Intel® 460GX Chipset System Software Developer’s Manual11.1.16 Deterministic Latency Control Register (Function 0)...11-7

System Architecture3-8 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 4-1System Address Map 44.1 Memory Map The Itanium™ processor supports a 44 bit address space. The 460

System Address Map4-2 Intel® 460GX Chipset Software Developer’s Manual4.1.1.4 System FirmwareThe 64 KB region from F_0000h to F_FFFFh is treated as a

Intel® 460GX Chipset Software Developer’s Manual 4-3System Address Map4.1.2 Low Extended Memory RegionThe 15 MB Low Extended Memory region is always m

System Address Map4-4 Intel® 460GX Chipset Software Developer’s Manual— FEB0_0CC0: This address is used for BSP selection. It is a write once register

Intel® 460GX Chipset Software Developer’s Manual 4-5System Address Map4.2 I/O Address MapThe 460GX chipset allows I/O addresses to be mapped to resour

System Address Map4-6 Intel® 460GX Chipset Software Developer’s Manual• I/O addresses used for VGA controllers: 03B0h-03BBh and 03C0h-03DFh. These add

Intel® 460GX Chipset Software Developer’s Manual 4-7System Address Map4.3 Devices View of the System Memory MapFigure 4-1 shows an Expander Bridge dev

System Address Map4-8 Intel® 460GX Chipset Software Developer’s Manual4.4 Legal and Illegal Address DispositionBelow is the disposition of addresses d

Intel® 460GX Chipset Software Developer’s Manual 4-9System Address MapNote: Accesses listed as “unclaimed” in the table for inbound transactions assum

Intel® 460GX Chipset System Software Developer’s Manual ix13.2.4 PCISTS–PCI Device Status Register (Function 2)...13-313.2.

System Address Map4-10 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 5-1Memory Subsystem 5The Intel 460GX chipset’s memory subsystem consists of the SAC’s DRAM controller

Memory Subsystem5-2 Intel® 460GX Chipset Software Developer’s ManualEach card is organized as 2 stacks of up to 4 rows each. A stack consists of 1 to

Intel® 460GX Chipset Software Developer’s Manual 5-3Memory SubsystemFigure 5-2 for an illustration. In theory all 4 of these lines could be transferri

Memory Subsystem5-4 Intel® 460GX Chipset Software Developer’s Manual5.2 Interleaving/ConfigurationsMaximum system bandwidth is obtainable in several w

Intel® 460GX Chipset Software Developer’s Manual 5-5Memory Subsystem5.2.1 Summary of Configuration RulesThe memory system may populate any row in any

Memory Subsystem5-6 Intel® 460GX Chipset Software Developer’s Manual5.4 Memory Subsystem ClockingThe DIMMs are clocked at half the system bus frequenc

Intel® 460GX Chipset Software Developer’s Manual 5-7Memory Subsystem5.5.3 Hardware InitializationIn order to decrease boot time of systems with large

Memory Subsystem5-8 Intel® 460GX Chipset Software Developer’s Manual

Intel® 460GX Chipset Software Developer’s Manual 6-1 Data Integrity and Error Handling 66.1 IntegrityThis chapter explains the various errors in the c