Intel GD82559ER User Manual Page 89
- Page / 94
- Table of contents
- BOOKMARKS
- GD82559ER Fast Ethernet** 1
- PCI Controller 1
- Revision History 2
- Contents 3
- 1. Introduction 7
- 2.1 Parallel Subs 9
- 2.2 FIFO Subs 10
- GD82559ER — Networkin 12
- Silicon 12
- Datasheet 12
- 3.2.1 Address and Data Si 13
- 3.2.2 Interface Control Si 14
- Interface Si 15
- 3.3 Local Memor 15
- 3.4 Testabilit 16
- Port Si 16
- 3.5 PHY Si 17
- 4.1 82559ER Initialization 19
- 4.2 PCI Interface 20
- 3421 56789 21
- ADDR DATA 22
- MEM RD BE# 22
- 4.2.1.1.3 Retr 23
- Premature Accesses 23
- 3421 5678910 25
- 4.2.1.2.1 Memor 26
- Write and Invalidate 26
- 4.2.1.2.2 Read Ali 27
- 4.2.1.2.3 Error Handlin 28
- 4.2.4 Power States 29
- 4.2.4.7.2 PCI Reset Si 32
- 4.2.5.1 “Interestin 33
- ” Packet Events 33
- 4.3 Parallel Flash Interface 34
- 4.4 Serial EEPROM Interface 34
- 4.5 10/100 Mb 36
- 5.5 TriState 40
- 5.6 Nand - Tree 40
- 6.1 100BASE-TX PHY Unit 43
- 6.1.2.4 Transmit Driver 45
- 6.2 10BASE-T Functionalit 47
- 6.2.3 10BASE-T Receive Blocks 48
- 6.3 Auto-Ne 49
- 6.4 LED Descri 51
- SpeedLED 52
- 7. PCI Confi 53
- 1015 01234567 54
- 7.1.3 PCI Status Register 55
- Reserved 58
- I/O space indicator 58
- 7.1.20 Data Re 62
- 8. Control/Status Registers 63
- 8.2 Statistical Counters 68
- 9. PHY Unit Registers 71
- Definitions 73
- 9.2 MDI Registers 8 - 15 74
- 9.3 MDI Register 16 - 31 74
- 10.1 Absolute Maximum Ratings 79
- 10.2 DC Specifications 79
- Rbias100 81
- 10.3 AC Specifications 82
- 10.4 Timing Specifications 83
- 10.4.2 Timing Parameters 84
- 10.4.2.2 PCI Timings 85
- 10.4.2.5 PHY Timings 88
- 12.1 Package Information 91
- 12.2 Pinout Information 92
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