Intel 41210 User Manual Page 64
- Page / 64
- Table of contents
- BOOKMARKS
- Design Guide 1
- Contents 3
- Revision History 5
- About This Document 1 7
- About This Document 8
- Introduction 2 9
- 2.3 Power Management 10
- 2.4 SMBus Interface 10
- 41210 Bridge 11
- Microcontroller 11
- 2.5 JTAG 12
- 2.6 Related Documents 12
- 2.7 Intel 13
- Applications 13
- Introduction 14
- Package Information 3 15
- Package Information 16
- Power Plane Layout 4 19
- B2714-01 20
- Capacitor Legend 20
- 0603-0.1 F 20
- 0603-1 F 20
- 1206-10 F 20
- 4.2 Split Voltage Planes 21
- B2715-01 22
- Considerations 5 23
- General Routing Guidelines 6 25
- 6.3 EMI Considerations 26
- 6.5 Trace Impedance 27
- 6.5.1 Differential Impedance 28
- B2716 -01 28
- B2717 -01 28
- Board Layout Guidelines 7 29
- Board Layout Guidelines 30
- PCI-X Layout Guidelines 8 31
- 8.2 PCI Arbitration 32
- B2718 -01 33
- Ω resistor 35
- PCI-X Layout Guidelines 36
- 8.6 Intel 38
- Guide Layout Analysis 38
- PCI Express Layout 9 45
- PCI Express Layout 47
- Circuit Implementations 10 49
- B2724 -01 50
- B2725 -01 51
- B2726 -01 52
- B2727 -01 53
- PE_RCOMP[0] 53
- PE_RCOMP[1] 53
- 10.2.1 SM Bus 54
- Boards 11 55
- 11.2 Material 56
- 11.3 Impedance 56
- 11.4 Board Outline 57
- Design Guide Checklist 12 59
- Design Guide Checklist 60
- •Pull up to 3.3V through a 61
- •Connect this pin to 61
- Table 24. JTAG Signals 64
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