Intel 8XC251SA User Manual

8XC251SA, 8XC251SB,8XC251SP, 8XC251SQEmbedded MicrocontrollerUsers Manual8XC251SA, 8XC251SB, 8XC251SP, 8XC251SQEmbedded Microcontroller Users Manual

8XC251SA, SB, SP, SQ USER’S MANUALviii12.2.2 Power Off Flag ...

8XC251SA, SB, SP, SQ USER’S MANUAL5-18.Figure 5-2. Program Status Word RegisterPSWAddress: S:D0HReset State: 0000 0000B7 0CY AC F0 RS1 RS0 OV UD PBit

5-19PROGRAMMING.Figure 5-3. Program Status Word 1 RegisterPSW1Address: S:D1HReset State: 0000 0000B7 0CY AC N RS1 RS0 OV Z —Bit NumberBit MnemonicFun

6Interrupt System

6-1CHAPTER 6INTERRUPT SYSTEM6.1 OVERVIEWThe 8XC251Sx, like other control-oriented computer architectures, employs a program interruptmethod. This oper

8XC251SA, SB, SP, SQ USER’S MANUAL6-2Figure 6-1. Interrupt Control System IE001INT0#Timer 0IE101INT1#Timer 10101ECFECCFxIT0IT15A4149-01IPInterrupt En

6-3INTERRUPT SYSTEM6.2 8XC251SA, SB, SP, SQ INTERRUPT SOURCESFigure 6-1 illustrates the interrupt control system. The 8XC251Sx has eight interrupt sou

8XC251SA, SB, SP, SQ USER’S MANUAL6-46.2.2 Timer InterruptsTwo timer-interrupt request bits TF0 and TF1 (see TCON register, Figure 8-6 on page 8-8) ar

6-5INTERRUPT SYSTEM6.3 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPTThe programmable counter array (PCA) interrupt is generated by the logical OR of five

CONTENTSixCHAPTER 14PROGRAMMING AND VERIFYINGNONVOLATILE MEMORY14.1 GENERAL...

8XC251SA, SB, SP, SQ USER’S MANUAL6-6 Figure 6-2. Interrupt Enable RegisterIE0Address: S:A8HReset State: 0000 0000B7 0EA EC ET2 ES ET1 EX1 ET0 E

6-7INTERRUPT SYSTEM6.6 INTERRUPT PRIORITIESEach of the seven 8XC251Sx interrupt sources may be individually programmed to one of fourpriority levels.

8XC251SA, SB, SP, SQ USER’S MANUAL6-8Figure 6-3. Interrupt Priority High RegisterFigure 6-4. Interrupt Priority Low RegisterIPH0Address: S:B7HReset

6-9INTERRUPT SYSTEM6.7 INTERRUPT PROCESSINGInterrupt processing is a dynamic operation that begins when a source requests an interrupt andlasts until

8XC251SA, SB, SP, SQ USER’S MANUAL6-106.7.1 Minimum Fixed Interrupt TimeAll interrupts are sampled or polled every four state times (see Figure 6-5).

6-11INTERRUPT SYSTEMtime is five states for internal interrupts and six states for external interrupts. External interrupts must remain active for at

8XC251SA, SB, SP, SQ USER’S MANUAL6-12Figure 6-7. Response Time Example #26.7.2.2 Computation of Worst-case Latency With VariablesWorst-case latency

6-13INTERRUPT SYSTEM6.7.2.3 Latency CalculationsAssume the use of a zero-wait-state external memory where current instructions, the ISR, and thestack

8XC251SA, SB, SP, SQ USER’S MANUAL6-146.7.2.4 Blocking ConditionsIf all enable and priority requirements have been met, a single prioritized interrupt

6-15INTERRUPT SYSTEM6.7.3 ISRs in ProcessISR execution proceeds until the RETI instruction is encountered. The RETI instruction informsthe processor t

8XC251SA, SB, SP, SQ USER’S MANUALxFIGURESFigure Page2-1 Functional Block Diagram of the 8XC251SA, SB, SP, SQ...

7Input/Output Ports

7-1CHAPTER 7INPUT/OUTPUT PORTS7.1 INPUT/OUTPUT PORT OVERVIEWThe 8XC251Sx uses input/output (I/O) ports to exchange data with external devices. In addi

8XC251SA, SB, SP, SQ USER’S MANUAL7-27.2 I/O CONFIGURATIONSEach port SFR operates via type-D latches, as illustrated in Figure 7-1 for ports 1 and 3.

7-3INPUT/OUTPUT PORTSFigure 7-1. Port 1 and Port 3 StructureFigure 7-2. Port 0 StructureReadLatchReadPinWrite toLatchInternalBusAlternateOutput

8XC251SA, SB, SP, SQ USER’S MANUAL7-4Figure 7-3. Port 2 StructureWhen port 0 and port 2 are used for an external memory cycle, an internal control si

7-5INPUT/OUTPUT PORTS7.5 READ-MODIFY-WRITE INSTRUCTIONSSome instructions read the latch data rather than the pin data. The latch based instructions re

8XC251SA, SB, SP, SQ USER’S MANUAL7-67.6 QUASI-BIDIRECTIONAL PORT OPERATIONPort 1, port 2, and port 3 have fixed internal pullups and are referred to

7-7INPUT/OUTPUT PORTSFigure 7-4. Internal Pullup Configurations 7.7 PORT LOADINGOutput buffers of port 1, port 2, and port 3 can each sink 1.6 mA at

CONTENTSxiFIGURESFigure Page8-12 T2CON: Timer 2 Control Register ...8-179-1

8XC251SA, SB, SP, SQ USER’S MANUAL7-8The 8XC251Sx CPU writes FFH to the P0 register for all external memory bus cycles. This over-writes previous info

7-9INPUT/OUTPUT PORTSNOTEAvoid MOV P0 instructions for external memory accesses. These instructions can corrupt input code bytes at port 0. External s

8Timer/Counters and Watchdog Timer

8-1CHAPTER 8TIMER/COUNTERS AND WATCHDOG TIMERThis chapter describes the timer/counters and the watchdog timer (WDT) included as peripheralson the 8XC2

8XC251SA, SB, SP, SQ USER’S MANUAL8-2 Figure 8-1. Basic Logic of the Timer/CountersThe C\Tx# control bit selects timer operation or counter

8-3TIMER/COUNTERS AND WATCHDOG TIMERFor timer operation (C/Tx# = 0), the timer register counts the divided-down system clock. Thetimer register is inc

8XC251SA, SB, SP, SQ USER’S MANUAL8-4For normal timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the se-lected input. Setting

8-5TIMER/COUNTERS AND WATCHDOG TIMER8.3.3 Mode 2 (8-bit Timer With Auto-reload)Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automat

8XC251SA, SB, SP, SQ USER’S MANUALxiiFIGURESFigure Page13-23 Bus Diagram for Example 4: 87C251SB/83C251SB in Nonpage Mode ...13-2413-24

8XC251SA, SB, SP, SQ USER’S MANUAL8-6Timer 1 is controlled by the four high-order bits of the TMOD register (Figure 8-5) and bits 7, 6,3, and 2 of the

8-7TIMER/COUNTERS AND WATCHDOG TIMER Figure 8-5. TMOD: Timer/Counter Mode Control RegisterTMODAddress: S:89HReset State: 0000 0000B7 0GATE1 C/T

8XC251SA, SB, SP, SQ USER’S MANUAL8-8 Figure 8-6. TCON: Timer/Counter Control RegisterWhen timer 0 is in mode 3, it uses timer 1’s overflow fla

8-9TIMER/COUNTERS AND WATCHDOG TIMER8.4.1 Mode 0 (13-bit Timer)Mode 0 configures timer 0 as a 13-bit timer, which is set up as an 8-bit timer (TH1 reg

8XC251SA, SB, SP, SQ USER’S MANUAL8-103. Enter an eight-bit reload value (nR) in register TH0. This can be the same as n0 ordifferent, depending on th

8-11TIMER/COUNTERS AND WATCHDOG TIMERTimer 2 provides the following operating modes: capture mode, auto-reload mode, baud rate gen-erator mode, and pr

8XC251SA, SB, SP, SQ USER’S MANUAL8-128.6.2 Auto-reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic

8-13TIMER/COUNTERS AND WATCHDOG TIMER8.6.2.2 Up/Down Counter OperationWhen DCEN = 1, timer 2 operates as an up/down counter (Figure 8-9). External pin

8XC251SA, SB, SP, SQ USER’S MANUAL8-148.6.3 Baud Rate Generator ModeThis mode configures timer 2 as a baud rate generator for use with the serial port

8-15TIMER/COUNTERS AND WATCHDOG TIMER Figure 8-10. Timer 2: Clock Out Mode . Table 8-3. Timer 2 Modes of OperationModeRCLK OR TCLK(in T2CON)CP

CONTENTSxiiiTABLESTable Page1-1 Intel Application Support Services...1-72

8XC251SA, SB, SP, SQ USER’S MANUAL8-16 Figure 8-11. T2MOD: Timer 2 Mode Control Register8.7 WATCHDOG TIMERThe peripheral section of the 8XC251Sx

8-17TIMER/COUNTERS AND WATCHDOG TIMER Figure 8-12. T2CON: Timer 2 Control RegisterT2CONAddress: S:C8HReset State: 0000 0000B7 0TF2 EXF2 RCLK TCL

8XC251SA, SB, SP, SQ USER’S MANUAL8-188.7.2 Using the WDT To use the WDT to recover from software malfunctions, the user program should control theWDT

9Programmable Counter Array

9-1CHAPTER 9PROGRAMMABLE COUNTER ARRAYThis chapter describes the programmable counter array (PCA), an on-chip peripheral of the8XC251Sx that performs

8XC251SA, SB, SP, SQ USER’S MANUAL9-29.1.1 Alternate Port UsagePCA modules 3 and 4 share port pins with the real-time wait state and address functions

9-3PROGRAMMABLE COUNTER ARRAYSetting the run control bit (CR in the CCON register) turns the PCA timer/counter on, if the out-put of the NAND gate (Fi

8XC251SA, SB, SP, SQ USER’S MANUAL9-4 Table 9-1. PCA Special Function Registers (SFRs)Mnemonic Description AddressCLCHPCA Timer/Counter. Thes

9-5PROGRAMMABLE COUNTER ARRAY9.3 PCA COMPARE/CAPTURE MODULESEach compare/capture module is made up of a compare/capture register pair(CCAPxH/CCAPxL),

8XC251SA, SB, SP, SQ USER’S MANUALxivTABLESTable Page10-4 Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 3...1

8XC251SA, SB, SP, SQ USER’S MANUAL9-6To program a compare/capture module for the 16-bit capture mode, program the CAPPx andCAPNx bits in the module’s

9-7PROGRAMMABLE COUNTER ARRAY9.3.2 Compare ModesThe compare function provides the capability for operating the five modules as timers, eventcounters,

8XC251SA, SB, SP, SQ USER’S MANUAL9-8 Figure 9-3. PCA Software Timer and High-speed Output Modes 9.3.4 High-speed Output ModeThe high-speed outpu

9-9PROGRAMMABLE COUNTER ARRAYThe user also has the option of generating an interrupt request when the match occurs by settingthe corresponding interru

8XC251SA, SB, SP, SQ USER’S MANUAL9-10The PCA WDT generates a reset signal each time a match occurs. To hold off a PCA WDT reset,the user has three op

9-11PROGRAMMABLE COUNTER ARRAY9.3.6 Pulse Width Modulation ModeThe five PCA comparator/capture modules can be independently programmed to function asp

8XC251SA, SB, SP, SQ USER’S MANUAL9-12The value in CCAPxL determines the duty cycle of the current period. The value in CCAPxH de-termines the duty cy

9-13PROGRAMMABLE COUNTER ARRAYFigure 9-7. CMOD: PCA Timer/Counter Mode RegisterCMODAddress: S:D9HReset State: 00XX X000B7 0CIDL WDTE — — — CPS1 CPS0

8XC251SA, SB, SP, SQ USER’S MANUAL9-14 Figure 9-8. CCON: PCA Timer/Counter Control Register CCONAddress: S:D8HReset State: 00X0 0000B7 0CF C

9-15PROGRAMMABLE COUNTER ARRAYFigure 9-9. CCAPMx: PCA Compare/Capture Module Mode RegistersCCAPMx (x = 0–4)Address: CCAPM0 S:DAHCCAPM1 S:DBHCCAPM2 S

CONTENTSxvTABLESTable PageC-4 Serial I/O SFRs ...

10Serial I/O Port

10-1CHAPTER 10SERIAL I/O PORTThe serial input/output port supports communication with modems and other external peripheraldevices. This chapter provid

8XC251SA, SB, SP, SQ USER’S MANUAL10-2 Figure 10-1. Serial Port Block DiagramTable 10-2. Serial Port Special Function RegistersMnemonic Descr

10-3SERIAL I/O PORTThe serial port control (SCON) register (Figure 10-2) configures and controls the serial port. Figure 10-2. SCON: Serial Por

8XC251SA, SB, SP, SQ USER’S MANUAL10-4 Figure 10-2. SCON: Serial Port Control Register (Continued)10.2 MODES OF OPERATIONThe serial I/O port can

10-5SERIAL I/O PORT Figure 10-3. Mode 0 Timing10.2.1.2 Reception (Mode 0)To start a reception in mode 0, write to the SCON register. Clear bits S

8XC251SA, SB, SP, SQ USER’S MANUAL10-610.2.2 Asynchronous Modes (Modes 1, 2, and 3)The serial port has three asynchronous modes of operation. • Mode 1

10-7SERIAL I/O PORT10.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3)Framing bit error detection is provided for the three asynchronous modes. To en

8XC251SA, SB, SP, SQ USER’S MANUAL10-8Implemented in hardware, automatic address recognition enhances the multiprocessor communi-cation feature by all

10-9SERIAL I/O PORTThe SADEN byte is selected so that each slave may be addressed separately. For Slave A, bit 0(the LSB) is a don't-care bit; fo

8XC251SA, SB, SP, SQ USER’S MANUAL10-1010.5.3 Reset AddressesOn reset, the SADDR and SADEN registers are initialized to 00H, i.e., the given and broad

10-11SERIAL I/O PORT10.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and 3)Timer 1 is the default baud rate generator for the transmitter and the receiv

8XC251SA, SB, SP, SQ USER’S MANUAL10-1210.6.3.3 Timer 2 Generated Baud Rates (Modes 1 and 3)Timer 2 may be selected as the baud rate generator for the

10-13SERIAL I/O PORTYou may configure timer 2 as a timer or a counter. In most applications, it is configured for timeroperation (i.e., the C/T2# bit

8XC251SA, SB, SP, SQ USER’S MANUAL10-14Note that timer 2 increments every state time (2TOSC) when it is in the baud rate generator mode.In the baud ra

11Minimum Hardware Setup

11-1CHAPTER 11MINIMUM HARDWARE SETUPThis chapter discusses the basic operating requirements of the MCS® 251 microcontroller and de-scribes a minimum h

1Guide to This Manual

8XC251SA, SB, SP, SQ USER’S MANUAL11-211.2 ELECTRICAL ENVIRONMENTThe 8XC251Sx is a high-speed CHMOS device. To achieve satisfactory performance, its o

11-3MINIMUM HARDWARE SETUP11.3 CLOCK SOURCESThe 8XC251Sx can obtain the system clock signal from an external clock source (Figure 11-3) orit can gener

8XC251SA, SB, SP, SQ USER’S MANUAL11-4For a more in-depth discussion of crystal specifications, ceramic resonators, and the selection ofC1 and C2 see

11-5MINIMUM HARDWARE SETUPFor external clock drive requirements, see the device data sheet. Figure 11-4 shows the clockdrive waveform. The external cl

8XC251SA, SB, SP, SQ USER’S MANUAL11-6The power off flag (POF) in the PCON register indicates whether a reset is a warm start or a coldstart. A cold s

11-7MINIMUM HARDWARE SETUPWhile the RST pin is high ALE, PSEN#, and the port pins are weakly pulled high. The first ALEoccurs 32TOSC after the reset s

8XC251SA, SB, SP, SQ USER’S MANUAL11-8 Figure 11-5. Reset Timing Sequence RSTXTALInternal ResetRoutineALEA4103-01PSEN#≥ 64 TOSC12332First ALE

12Special Operating Modes

12-1CHAPTER 12SPECIAL OPERATING MODESThis chapter describes the power control (PCON) register and three special operating modes: idle,powerdown, and o

8XC251SA, SB, SP, SQ USER’S MANUAL12-2 Figure 12-1. Power Control (PCON) RegisterPCONAddress: S:87HReset State: 00XX 0000B7 0SMOD1 SMOD0 — POF GF

12-3SPECIAL OPERATING MODES Figure 12-2. Idle and Powerdown Clock ControlTable 12-1. Pin Conditions in Various ModesModeProgram MemoryALEPi

8XC251SA, SB, SP, SQ USER’S MANUAL12-412.3 IDLE MODEIdle mode is a power reduction mode that reduces power consumption to about 40% of normal.In this

12-5SPECIAL OPERATING MODES12.3.2 Exiting Idle ModeThere are two ways to exit idle mode: • Generate an enabled interrupt. Hardware clears the PCON reg

8XC251SA, SB, SP, SQ USER’S MANUAL12-612.4.1 Entering Powerdown ModeTo enter powerdown mode, set the PCON register PD bit. The 8XC251Sx enters the pow

12-7SPECIAL OPERATING MODES12.5 ON-CIRCUIT EMULATION (ONCE) MODEThe on-circuit emulation (ONCE) mode permits external testers to test and debug 8XC251

13External Memory Interface

13-1CHAPTER 13EXTERNAL MEMORY INTERFACE13.1 OVERVIEWThe external memory interface comprises the external bus (ports 0 and 2, and when enabled alsoincl

1-1CHAPTER 1GUIDE TO THIS MANUALThis manual describes the 8XC251SA, SB, SP, SQ† embedded microcontroller, which is the firstmember of the Intel MCS® 2

8XC251SA, SB, SP, SQ USER’S MANUAL13-2 Table 13-1. External Memory Interface SignalsSignalNameType DescriptionAlternateFunctionA17 O Address Lin

13-3EXTERNAL MEMORY INTERFACE13.2 EXTERNAL BUS CYCLESThe section describes the bus cycles the 8XC251Sx executes to fetch code, read data, and writedat

8XC251SA, SB, SP, SQ USER’S MANUAL13-413.2.2 Nonpage Mode Bus CyclesIn nonpage mode, the external bus structure is the same as for MCS 51 microcontrol

13-5EXTERNAL MEMORY INTERFACE Figure 13-4. External Data Write (Nonpage Mode) 13.2.3 Page Mode Bus CyclesPage mode increases performance by reducing

8XC251SA, SB, SP, SQ USER’S MANUAL13-6Figure 13-5 shows the two types of external bus cycles for code fetches in page mode. The page-miss cycle is the

13-7EXTERNAL MEMORY INTERFACE Figure 13-6. External Data Read (Page Mode) Figure 13-7. External Data Write (Page Mode) A17/A16/P0P2ALERD#/PSEN

8XC251SA, SB, SP, SQ USER’S MANUAL13-813.3 WAIT STATESThe 8XC251SA, SB, SP, SQ provides three types of wait state solutions to external memory prob-le

13-9EXTERNAL MEMORY INTERFACE Figure 13-8. External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State) Figure 13-9. External Data Write (Nonp

8XC251SA, SB, SP, SQ USER’S MANUAL13-1013.4.2 Extending ALEFigure 13-10 shows the nonpage mode code fetch external bus cycle with ALE extended. Thewai

13-11EXTERNAL MEMORY INTERFACEFigure 13-11. Real-time Wait State Control Register (WCON) NOTEThe WAIT# and WCLK signals are alternate functions for t

8XC251SA, SB, SP, SQ USER’S MANUAL1-2Chapter 7, “Input/Output Ports” — describes the four 8-bit I/O ports (ports 0–3) and discussestheir configuration

8XC251SA, SB, SP, SQ USER’S MANUAL13-1213.5.1 Real-time WAIT# Enable (RTWE)The real-time WAIT# input is enabled by writing a logical ‘1’ to the WCON.0

13-13EXTERNAL MEMORY INTERFACEFigure 13-12. External Code Fetch/Data Read (Nonpage Mode, RT Wait State)Figure 13-13. External Data Write (Nonpage Mo

8XC251SA, SB, SP, SQ USER’S MANUAL13-14Figure 13-14. External Data Read (Page Mode, RT Wait State)Figure 13-15. External Data Write (Page Mode, RT W

13-15EXTERNAL MEMORY INTERFACE13.6 CONFIGURATION BYTE BUS CYCLESIf EA# = 0, devices obtain configuration information from a configuration array in ext

8XC251SA, SB, SP, SQ USER’S MANUAL13-1613.7 PORT 0 AND PORT 2 STATUSThis section summarizes the status of the port 0 and port 2 pins when these ports

13-17EXTERNAL MEMORY INTERFACE13.7.2 Port 0 and Port 2 Pin Status in Page ModeIn a page-mode bus cycle, the data is multiplexed with the upper address

8XC251SA, SB, SP, SQ USER’S MANUAL13-1813.8 EXTERNAL MEMORY DESIGN EXAMPLES This section presents several external memory designs for 8XC251Sx systems

13-19EXTERNAL MEMORY INTERFACE Figure 13-18. Address Space for Example 1 A4220-021056 Bytes On-chip RAM01:00:FE:FF:128 Kbytes External FlashAddres

8XC251SA, SB, SP, SQ USER’S MANUAL13-2013.8.2 Example 2: RD1:0 = 01, 17-bit Bus, External Flash and RAMIn this example, an 80C251SB operates in page m

13-21EXTERNAL MEMORY INTERFACE Figure 13-20. Address Space for Example 2 A4168-031056 Bytes On-chip RAM01:00:FE:FF:64 Kbytes External FlashAddres

1-3GUIDE TO THIS MANUALAppendix B, “Signal Descriptions” — describes the function(s) of each device pin. Descrip-tions are listed alphabetically by si

8XC251SA, SB, SP, SQ USER’S MANUAL13-2213.8.3 Example 3: RD1:0 = 01, 17-bit Bus, External RAMIn this example, an 87C251SB/83C251SB operates in nonpage

13-23EXTERNAL MEMORY INTERFACE Figure 13-22. Address Space for Example 3 A4169-031056 Bytes On-chip RAM01:00:FE:FF:16 Kbytes On-chip Code MemoryAd

8XC251SA, SB, SP, SQ USER’S MANUAL13-2413.8.4 Example 4: RD1:0 = 10, 16-bit Bus, External RAMIn this example, an 87C251SB/83C251SB operates in nonpage

13-25EXTERNAL MEMORY INTERFACE Figure 13-24. Address Space for Example 4 A4224-021056 Bytes On-chip RAM01:00:FE:FF:16 Kbytes On-chip Code MemoryAd

8XC251SA, SB, SP, SQ USER’S MANUAL13-2613.8.5 Example 5: RD1:0 = 11, 16-bit Bus, External EPROM and RAM In this example, an 80C251SB operates in nonpa

13-27EXTERNAL MEMORY INTERFACE Figure 13-25. Bus Diagram for Example 5: 80C251SB in Nonpage Mode A4145-01A7:0LatchA15:8A/D7:0EPROM(64 Kbytes)OE#C

8XC251SA, SB, SP, SQ USER’S MANUAL13-28 Figure 13-26. Address Space for Examples 5 and 6 1056 BytesOn-chip RAM01:00:FE:FF:64 Kbytes External EPR

13-29EXTERNAL MEMORY INTERFACE13.8.6 Example 6: RD1:0 = 11, 16-bit Bus, External EPROM and RAMIn this example, an 80C251SB operates in page mode with

8XC251SA, SB, SP, SQ USER’S MANUAL13-3013.8.7 Example 7: RD1:0 = 01, 17-bit Bus, External FlashIn this example, an 80C251SB operates in page mode with

14Programming and Verifying Nonvolatile Memory

8XC251SA, SB, SP, SQ USER’S MANUAL1-4Instructions Instruction mnemonics are shown in upper case to avoid confusion.When writing code, either upper cas

14-1CHAPTER 14PROGRAMMING AND VERIFYINGNONVOLATILE MEMORYThis chapter provides instructions for programming and verifying on-chip nonvolatile memoryon

8XC251SA, SB, SP, SQ USER’S MANUAL14-2In some microcontroller applications, it is desirable that user program code be secure from unau-thorized access

14-3PROGRAMMING AND VERIFYING NONVOLATILE MEMORY14.1.2 EPROM DevicesOn EPROM devices, the quartz window must be covered with an opaque label when the

8XC251SA, SB, SP, SQ USER’S MANUAL14-4 Table 14-1. Programming and Verifying Modes Mode RST PSEN# VPP PROG# Port0Port2AddressPort 1 (high)Port 3

14-5PROGRAMMING AND VERIFYING NONVOLATILE MEMORY Figure 14-1. Setup for Programming and Verifying Nonvolatile Memory 14.4 PROGRAMMING ALGORITHMT

8XC251SA, SB, SP, SQ USER’S MANUAL14-6 Figure 14-2. Program/Verify Bus Cycles 14.5 VERIFY ALGORITHMUse this procedure to verify user program code

14-7PROGRAMMING AND VERIFYING NONVOLATILE MEMORY14.6.1 On-chip Code MemoryOn-chip code memory is located in the top region of the memory space startin

8XC251SA, SB, SP, SQ USER’S MANUAL14-8 14.6.4 Encryption ArrayThe 87C251Sx and 83C251Sx controllers include a 128-byte encryption array located in

14-9PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 14.7 VERIFYING THE 83C251SA, SB, SP, SQ (ROM)Nonvolatile memory on the 83C251Sx controller is facto

1-5GUIDE TO THIS MANUALUnits of Measure The following abbreviations are used to represent units of measure:A amps, amperesDCV direct current voltsKbyt

AInstruction Set Reference

A-1APPENDIX AINSTRUCTION SET REFERENCEThis appendix contains reference material for the instructions in the MCS® 251 architecture. Itincludes an opcod

8XC251SA, SB, SP, SQ USER’S MANUALA-2A.1 NOTATION FOR INSTRUCTION OPERANDS Table A-1. Notation for Register OperandsRegister NotationMCS® 251Arch.MCS

A-3INSTRUCTION SET REFERENCETable A-2. Notation for Direct AddressesDirectAddress.DescriptionMCS® 251Arch.MCS 51Arch.dir8 An 8-bit direct address. Th

8XC251SA, SB, SP, SQ USER’S MANUALA-4A.2 OPCODE MAP AND SUPPORTING TABLESTable A-6. Instructions for MCS® 51 MicrocontrollersBin. 0 1 2 3 4 5 6-7 8-F

A-5INSTRUCTION SET REFERENCE Table A-7. New Instructions for the MCS® 251 ArchitectureBin. A5x8A5x9A5xAA5xBA5xCA5xDA5xEA5xFSrc.x8x9xAxBxCx

8XC251SA, SB, SP, SQ USER’S MANUALA-6 Table A-8. Data InstructionsInstruction Byte 0 Byte 1 Byte 2 Byte 3Oper Rmd,Rms x C md msOper WRjd,WRjs x D

A-7INSTRUCTION SET REFERENCEAll of the bit instructions in the MCS 251 architecture (Table A-7) have opcode A9, which servesas an escape byte (similar

8XC251SA, SB, SP, SQ USER’S MANUAL1-61.3.1 Data Sheet The data sheet is included in Embedded Microcontrollers and is also available individually.8XC25

8XC251SA, SB, SP, SQ USER’S MANUALA-8Table A-12. PUSH/POP Instructions Instruction Byte 0(x) Byte 1 Byte 2 Byte 3PUSH #data C A 0000 0010 #dataPUSH

A-9INSTRUCTION SET REFERENCETable A-14. Displacement/Extended MOVsInstruction Byte 0 Byte 1 Byte 2 Byte 3MOV Rm,@WRj+dis 0 9 m j/2 dis[15:8] dis[7:0

8XC251SA, SB, SP, SQ USER’S MANUALA-10Table A-15. INC/DECInstruction Byte 0 Byte 11 INC Rm,#short 0 B m 00 ss2 INC WRj,#short 0 B j/2 01 ss3 INC

A-11INSTRUCTION SET REFERENCEA.3 INSTRUCTION SET SUMMARYThis section summarizes the MCS 251 architecture instruction set. Tables A-19 through A-27 lis

8XC251SA, SB, SP, SQ USER’S MANUALA-12Table A-18. State Times to Access the Port SFRsInstructionCase 0Execution TimesAdditional State TimesBinary Sou

A-13INSTRUCTION SET REFERENCEORL CY,/bit51 1 1 1 2 3 4ORL dir8,#data 3 3 1 2 3 4ORL dir8,A 2 2 2 4 6 8ORL Rm,dir8 3 2 1 2 3 4SETB bit 432468SETB bit51

8XC251SA, SB, SP, SQ USER’S MANUALA-14A.3.2 Instruction Summaries Table A-19. Summary of Add and Subtract InstructionsAdd ADD <dest>,<

A-15INSTRUCTION SET REFERENCE Table A-20. Summary of Compare InstructionsCompare CMP <dest>,<src> dest opnd – src opndMnemonic <dest

8XC251SA, SB, SP, SQ USER’S MANUALA-16 Table A-21. Summary of Increment and Decrement InstructionsIncrement INC DPTR (DPTR)

A-17INSTRUCTION SET REFERENCETable A-23. Summary of Logical Instructions Logical AND ANL <dest>,<src> dest opnd ←dest opnd Λ src opndLogi

1-7GUIDE TO THIS MANUAL1.4 APPLICATION SUPPORT SERVICESYou can get up-to-date technical information from a variety of electronic support systems: theW

8XC251SA, SB, SP, SQ USER’S MANUALA-18SRARm Shift byte reg right through the MSB 3 2 2 1WRj Shift word reg right through the MSB 3 2 2 1SRLRm Shift by

A-19INSTRUCTION SET REFERENCETable A-24. Summary of Move Instructions Move (2) MOV <dest>,<src> destination ← src opndMove with Sign Exte

8XC251SA, SB, SP, SQ USER’S MANUALA-20MOVDRk,dir8 Dir addr to dword reg 4 6 3 5DRk,dir16 Dir addr (64K) to dword reg 5 6 4 5Rm,dir8 Dir addr to byte r

A-21INSTRUCTION SET REFERENCEMOV@WRj+dis16,WRj Word reg to Indir addr with disp (64K) 5 7 4 6@DRk+dis24,Rm Byte reg to Indir addr with disp (16M) 5 7

8XC251SA, SB, SP, SQ USER’S MANUALA-22Table A-25. Summary of Exchange, Push, and Pop Instructions Exchange Contents XCH <dest>,<src> A ↔

A-23INSTRUCTION SET REFERENCETable A-26. Summary of Bit Instructions Clear Bit CLR bit bit ← 0Set Bit SETB bit bit ← 1Complement Bit CPL bit bit← Øbi

8XC251SA, SB, SP, SQ USER’S MANUALA-24Table A-27. Summary of Control Instructions Mnemonic <dest>,<src> NotesBinary Mode Source ModeBytes

A-25INSTRUCTION SET REFERENCEJSLE rel Jump if less than or equal (signed) 3 2/5 2 1/4JSG rel Jump if greater than (signed) 3 2/5 2 1/4JSGE rel Jump i

8XC251SA, SB, SP, SQ USER’S MANUALA-26A.4 INSTRUCTION DESCRIPTIONSThis section describes each instruction in the MCS 251 architecture. See the note on

A-27INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: ACALL (PC) ← (PC) + 2 (SP) ← (SP) + 1 ((SP)) ←

8XC251SA, SB, SP, SQ USER’S MANUAL1-81.4.3 FaxBack ServiceThe FaxBack service is an on-demand publishing system that sends documents to your fax ma-ch

8XC251SA, SB, SP, SQ USER’S MANUALA-28Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: ADD (A) ← (A) + #dataADD A,dir8Binary Mo

A-29INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: ADD (Rmd) ← (Rmd) + (Rms) ADD WRjd,WRjs

8XC251SA, SB, SP, SQ USER’S MANUALA-30ADD WRj,#data16Binary Mode Source ModeBytes: 54States: 43[Encoding] Hex Code in: Binary Mode = [A5][Encoding]Sou

A-31INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [A5][Encoding]Source Mode = [EncodingOperation: ADD (WRj) ← (WRj) + (dir8)ADD Rm,dir16Binary M

8XC251SA, SB, SP, SQ USER’S MANUALA-32ADD Rm,@DRkBinary Mode Source ModeBytes: 43States: 43[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source M

A-33INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: ADDC (A) ← (A) + (CY) + #data ADDC A,dir8Binary

8XC251SA, SB, SP, SQ USER’S MANUALA-34AJMP addr11 Function: Absolute jump Description: Transfers program execution to the specified address, which is

A-35INSTRUCTION SET REFERENCEExample: Register 1 contains 0C3H (11000011B) and register 0 contains 55H (01010101B). After executing the instruction AN

8XC251SA, SB, SP, SQ USER’S MANUALA-36Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: ANL (A) ← (A) Λ #data ANL A,dir8Binary M

A-37INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: ANL (Rmd) ← (Rmd) Λ (Rms) ANL WRjd,WRjsBi

1-9GUIDE TO THIS MANUALAny customer with a PC and modem can access the BBS. The system provides automatic config-uration support for 1200- through 192

8XC251SA, SB, SP, SQ USER’S MANUALA-38ANL Rm,dir8Binary Mode Source ModeBytes: 43States: 3† 2††If this instruction addresses a port (Px, x = 0–3), add

A-39INSTRUCTION SET REFERENCE[Encoding] Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: ANL (WRj) ← (WRj) Λ (dir16)ANL Rm,

8XC251SA, SB, SP, SQ USER’S MANUALA-40Flags:Example: Set the CY flag if, and only if, P1.0 = 1, ACC. 7 = 1, and OV = 0: MOV CY,P1.0 ;Load carry with

A-41INSTRUCTION SET REFERENCEOperation: ANL (CY) ← (CY) Λ (bit) ANL CY,/bitBinary Mode Source ModeBytes: 43States: 3† 2††If this instruction addresses

8XC251SA, SB, SP, SQ USER’S MANUALA-42VariationsCJNE A,#data,rel Binary Mode Source ModeNot Taken Taken Not Taken TakenBytes: 33 33States: 25 25Hex Co

A-43INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding]Source Mode = [A5][Encoding]Operation: (PC) ← (PC) + 3IF ((Ri)) ≠ #dataTHEN (PC

8XC251SA, SB, SP, SQ USER’S MANUALA-44Binary Mode Source ModeBytes: 11States: 11Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation

A-45INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: CLR (CY) ← 0 CLR bitBinary Mode Source ModeBytes:

8XC251SA, SB, SP, SQ USER’S MANUALA-46 Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: CMP(Rmd) – (Rms) CMP WRjd,WRjs

A-47INSTRUCTION SET REFERENCECMP WRj,#data16Binary Mode Source ModeBytes: 54States: 43[Encoding] Hex Code in: Binary Mode = [A5][Encoding]Source Mode

May 1996 Order Number 272795-0028XC251SA, 8XC251SB, 8XC251SP, 8XC251SQEmbedded MicrocontrollerUser’s Manual

8XC251SA, SB, SP, SQ USER’S MANUALA-48 Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: CMP (Rm) – (dir8) CMP WRj,dir8B

A-49INSTRUCTION SET REFERENCECMP Rm,@WRjBinary Mode Source ModeBytes: 43States: 32[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [En

8XC251SA, SB, SP, SQ USER’S MANUALA-50Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: CPL (A) ← Ø(A)CPL bit Function: Compleme

A-51INSTRUCTION SET REFERENCEOperation: CPL (CY) ← Ø(CY)CPL bitBinary Mode Source ModeBytes: 43States: 4† 3††If this instruction addresses a port (Px,

8XC251SA, SB, SP, SQ USER’S MANUALA-52Example: The accumulator contains 56H (01010110B), which represents the packed BCD digits of the decimal number

A-53INSTRUCTION SET REFERENCEExample: Register 0 contains 7FH (01111111B). On-chip RAM locations 7EH and 7FH contain 00H and 40H, respectively. After

8XC251SA, SB, SP, SQ USER’S MANUALA-54DEC RnBinary Mode Source ModeBytes: 12States: 12Hex Code in: Binary Mode = [Encoding]Source Mode = [A5][Encoding

A-55INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: DEC (WRj) ← (WRj) – #shortDEC DRk,#shortB

8XC251SA, SB, SP, SQ USER’S MANUALA-56VariationsDIV Rmd RmsBinary Mode Source ModeBytes: 32States: 11 10Hex Code in: Binary Mode = [A5][Encoding]Sourc

A-57INSTRUCTION SET REFERENCEException: if register B contains 00H, the values returned in the accumulator and register B are undefined; the CY flag i

2Architectural Overview

8XC251SA, SB, SP, SQ USER’S MANUALA-58Example: The on-chip RAM locations 40H, 50H, and 60H contain 01H, 70H, and 15H, respectively. After executing th

A-59INSTRUCTION SET REFERENCEOperation: DJNZ (PC) ← (PC) + 2 (Rn) ← (Rn) – 1 IF (Rn) > 0 or (Rn) < 0 THEN (PC) ← (PC)

8XC251SA, SB, SP, SQ USER’S MANUALA-60ECALL @DRkBinary Mode Source ModeBytes: 32States: 12 11Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [E

A-61INSTRUCTION SET REFERENCEEJMP @DRkBinary Mode Source ModeBytes: 32States: 76Hex Code in: Binary Mode = [A5] [Encoding]Source Mode = [Encoding]Oper

8XC251SA, SB, SP, SQ USER’S MANUALA-62Flags:Example: Register 0 contains 7EH (011111110B) and on-chip RAM locations 7EH and 7FH contain 0FFH and 40H,

A-63INSTRUCTION SET REFERENCEOperation: INC ((Ri) ← ((Ri)) + 1 INC RnBinary Mode Source ModeBytes: 12States: 12Hex Code in: Binary Mode = [Encoding]So

8XC251SA, SB, SP, SQ USER’S MANUALA-64Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: INC (WRj) ← (WRj) + #shortINC DRk,#s

A-65INSTRUCTION SET REFERENCEJB bit51,rel JB bit,relFunction: Jump if bit set Description: If the specified bit is a one, jump to the address specifie

8XC251SA, SB, SP, SQ USER’S MANUALA-66Operation: JB (PC) ← (PC) + 3 IF (bit) = 1 THEN (PC) ← (PC) + relJBC bit51,rel JBC bit

A-67INSTRUCTION SET REFERENCEJBC bit,relBinary Mode Source ModeNot Taken Taken Not Taken TakenBytes: 5 5 4 4States: 47 36[Encoding]Hex Code in: Binary

8XC251SA, SB, SP, SQ USER’S MANUALA-68Operation: JC (PC) ← (PC) + 2 IF (CY) = 1 THEN (PC) ← (PC) + rel JE rel Function: Jump if

A-69INSTRUCTION SET REFERENCEExample: The instructionJG LABEL1 causes program execution to continue at label LABEL1 if the Z flag and the CY flag are

8XC251SA, SB, SP, SQ USER’S MANUALA-70Operation: JLE(PC) ← (PC) + 2 IF (Z) = 1 OR (CY) = 1 THEN (PC) ← (PC) + rel JMP @A+DPTR Function: Jump

A-71INSTRUCTION SET REFERENCEFlags:Example: Input port 1 contains 11001010B and the accumulator contains 56H (01010110B). After executing the instruct

8XC251SA, SB, SP, SQ USER’S MANUALA-72JNC rel Function: Jump if carry not set Description: If the CY flag is clear, branch to the address specified; o

A-73INSTRUCTION SET REFERENCEBinary Mode Source ModeNot Taken Taken Not Taken TakenBytes: 33 22States: 25 14Hex Code in: Binary Mode = [A5][Encoding]S

8XC251SA, SB, SP, SQ USER’S MANUALA-74JSG rel Function: Jump if greater than (signed)Description: If the Z flag is clear AND the N flag and the OV fla

A-75INSTRUCTION SET REFERENCEBinary Mode Source ModeNot Taken Taken Not Taken TakenBytes: 33 22States: 25 14Hex Code in: Binary Mode = [A5][Encoding]S

8XC251SA, SB, SP, SQ USER’S MANUALA-76JSLE rel Function: Jump if less than or equal (signed)Description: If the Z flag is set OR if the the N flag and

A-77INSTRUCTION SET REFERENCEExample: The accumulator contains 01H. After executing the instruction sequence JZ LABEL1DEC A JZ LABEL2 the accumulator

2-1CHAPTER 2ARCHITECTURAL OVERVIEWThe 8XC251Sx is the first member of the MCS®251 microcontroller family. This family of 8-bitmicrocontrollers is a hi

8XC251SA, SB, SP, SQ USER’S MANUALA-78Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding]Operation: LCALL (PC) ← (PC) + 3 (SP) ← (SP) + 1

A-79INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [Encoding] Source Mode = [Encoding]Operation: LJMP (PC) ← (addr.15:0)LJMP @WRj Binary Mode So

8XC251SA, SB, SP, SQ USER’S MANUALA-80Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding]Operation: MOV (A) ← #data MOV dir8,#data Binary

A-81INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding]Operation: MOV (dir8) ← (dir8) MOV dir8,@Ri Binary Mod

8XC251SA, SB, SP, SQ USER’S MANUALA-82MOV Rn,dir8 Binary Mode Source ModeBytes: 23States: 1† 2††If this instruction addresses a port (Px, x = 0–3), ad

A-83INSTRUCTION SET REFERENCEOperation: MOV (A) ← (Rn) MOV dir8,A Binary Mode Source ModeBytes: 22States: 2† 2††If this instruction addresses a port (

8XC251SA, SB, SP, SQ USER’S MANUALA-84Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV (Rmd) ← (Rms) MOV WRjd,WRjs Bi

A-85INSTRUCTION SET REFERENCE[Encoding]Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV (WRj) ← #data16 MOV DRk,#0dat

8XC251SA, SB, SP, SQ USER’S MANUALA-86Operation: MOV (Rm) ← (dir8)MOV WRj,dir8 Binary Mode Source ModeBytes: 43States: 43Hex Code in: Binary Mode = [

A-87INSTRUCTION SET REFERENCE[Encoding]Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV (WRj) ← (dir16)MOV DRk,dir16 B

8XC251SA, SB, SP, SQ USER’S MANUAL2-2 Figure 2-1. Functional Block Diagram of the 8XC251SA, SB, SP, SQ SRC2 (8)Code Address (24)Clock & Reset

8XC251SA, SB, SP, SQ USER’S MANUALA-88MOV WRjd,@WRjs Binary Mode Source ModeBytes: 43States: 43[Encoding]Hex Code in: Binary Mode = [A5][Encoding] So

A-89INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV (dir8) ← (WRj) MOV dir8,DRk Binary Mo

8XC251SA, SB, SP, SQ USER’S MANUALA-90MOV dir16,DRk Binary Mode Source ModeBytes: 54States: 76[Encoding]Hex Code in: Binary Mode = [A5][Encoding] Sou

A-91INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV ((WRjd)) ← (WRjs)MOV @DRk,WRj Binary Mo

8XC251SA, SB, SP, SQ USER’S MANUALA-92MOV Rm,@DRk + dis24 Binary Mode Source ModeBytes: 54States: 76[Encoding]Hex Code in: Binary Mode = [A5][Encodin

A-93INSTRUCTION SET REFERENCE[Encoding]Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV ((WRj)) + (dis) ← (WRj)MOV @D

8XC251SA, SB, SP, SQ USER’S MANUALA-94Example: The CY flag is set, input Port 3 contains 11000101B, and output Port 1 contains 35H (00110101B). After

A-95INSTRUCTION SET REFERENCEOperation: MOV (bit) ← (CY)MOV CY,bitBinary Mode Source ModeBytes: 43States: 3† 2††If this instruction addresses a port (

8XC251SA, SB, SP, SQ USER’S MANUALA-96MOVC A,@A+<base–reg> Function: Move code byte Description: Loads the accumulator with a code byte or const

A-97INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: MOVC (A) ← ((A) + (DPTR)) MOVH DRk,#data16Functio

2-3ARCHITECTURAL OVERVIEW2.1 8XC251SA, SB, SP, SQ ARCHITECTUREFigure 2-1 is a functional block diagram of the 8XC251SA, SB, SP, SQ. The core, which is

8XC251SA, SB, SP, SQ USER’S MANUALA-98Example: Eight-bit register Rm contains 055H (01010101B) and the 16-bit register WRj contains 0FFFFH (11111111 1

A-99INSTRUCTION SET REFERENCEExample: The MCS 251 controller is operating in nonpage mode. An external 256-byte RAM using multiplexed address/data lin

8XC251SA, SB, SP, SQ USER’S MANUALA-100MOVX @Ri,A Binary Mode Source ModeBytes: 11States: 44Hex Code in: Binary Mode = [Encoding]Source Mode = [A5][En

A-101INSTRUCTION SET REFERENCEMUL <dest>,<src>Function: MultiplyDescription: Multiplies the unsigned integer in the source register with t

8XC251SA, SB, SP, SQ USER’S MANUALA-102MUL WRjd,WRjsBinary Mode Source ModeBytes: 32States: 12 11Hex Code in: Binary Mode = [A5][Encoding]Source Mode

A-103INSTRUCTION SET REFERENCENOP Function: No operation Description: Execution continues at the following instruction. Affects the PC register only.

8XC251SA, SB, SP, SQ USER’S MANUALA-104Example: The accumulator contains 0C3H (11000011B) and R0 contains 55H (01010101B). After executing the instruc

A-105INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: ORL (A) ← (A) V #dataORL A,dir8Binary Mode Sourc

8XC251SA, SB, SP, SQ USER’S MANUALA-106Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: ORL (Rmd) ← (Rmd) V (Rms) ORL WRjd,

A-107INSTRUCTION SET REFERENCEORL Rm,dir8Binary Mode Source ModeBytes: 43States: 3† 2††If this instruction addresses a port (Px, x = 0–3), add 1 state

8XC251SA, SB, SP, SQ USER’S MANUAL2-4The 8XC251Sx has two power-saving modes. In idle mode, the CPU clock is stopped, whileclocks to the peripherals c

8XC251SA, SB, SP, SQ USER’S MANUALA-108[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: ORL (WRj) ← (WRj) V (dir1

A-109INSTRUCTION SET REFERENCEExample: Set the CY flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0: MOV CY,P1.0 ;LOAD CARRY WITH INPUT

8XC251SA, SB, SP, SQ USER’S MANUALA-110ORL CY,/bitBinary Mode Source ModeBytes: 43States: 3† 2††If this instruction addresses a port (Px, x = 0–3), ad

A-111INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: POP (dir8) ← ((SP)) (SP) ← (SP) – 1 POP RmBinary

8XC251SA, SB, SP, SQ USER’S MANUALA-112PUSH <dest>Function: Push onto stack Description: Increments the stack pointer by one. The contents of th

A-113INSTRUCTION SET REFERENCEPUSH #data16Binary Mode Source ModeBytes: 54States: 65[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [

8XC251SA, SB, SP, SQ USER’S MANUALA-114PUSH DRkBinary Mode Source ModeBytes: 32States: 98Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encod

A-115INSTRUCTION SET REFERENCERETI Function: Return from interrupt Description: This instruction pops two or four bytes from the stack, depending on t

8XC251SA, SB, SP, SQ USER’S MANUALA-116Operation for INTR = 1:RETI(PC).15:8 ← ((SP))(SP) ← (SP) – 1 PC).7:0 ← ((SP)) (SP) ← (SP) – 1 (PC).23:16 ← ((SP

A-117INSTRUCTION SET REFERENCEExample: The accumulator contains 0C5H (11000101B) and the CY flag is clear. After executing the instruction RLC A the a

2-5ARCHITECTURAL OVERVIEW2.2.1 CPUFigure 2-2 is a functional block diagram of the CPU (central processor unit). The 8XC251Sxfetches instructions from

8XC251SA, SB, SP, SQ USER’S MANUALA-118RRC A Function: Rotate accumulator right through carry flag Description: Rotates the eight bits in the accumula

A-119INSTRUCTION SET REFERENCESETB bit51Binary Mode Source ModeBytes: 22States: 2† 2††If this instruction addresses a port (Px, x = 0–3), add 2 states

8XC251SA, SB, SP, SQ USER’S MANUALA-120Flags:Example: The label "RELADR" is assigned to an instruction at program memory location 0123H. The

A-121INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: SLL(Rm).a+1 ← (Rm).a (Rm).0 ← 0 CY ← (Rm).7S

8XC251SA, SB, SP, SQ USER’S MANUALA-122SRA WRjBinary Mode Source ModeBytes: 32States: 21Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encodi

A-123INSTRUCTION SET REFERENCESRL WRjBinary Mode Source ModeBytes: 32States: 21Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operat

8XC251SA, SB, SP, SQ USER’S MANUALA-124Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: SUB(Rmd) ← (Rmd) – (Rms) SUB WRjd,W

A-125INSTRUCTION SET REFERENCE[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: SUB (WRj) ← (WRj) – #data16 SUB DR

8XC251SA, SB, SP, SQ USER’S MANUALA-126SUB Rm,dir16Binary Mode Source ModeBytes: 54States: 32[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source

A-127INSTRUCTION SET REFERENCE[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: SUB (Rm) ← (Rm) – ((DRk))SUBB A,&l

8XC251SA, SB, SP, SQ USER’S MANUAL2-62.2.2 Clock and Reset UnitThe timing source for the 8XC251Sx can be an external oscillator or an internal oscilla

8XC251SA, SB, SP, SQ USER’S MANUALA-128 Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: SUBB (A) ← (A) – (CY) – #dataSUBB A

A-129INSTRUCTION SET REFERENCESWAP A Function: Swap nibbles within the accumulator Description: Interchanges the low and high nibbles (4-bit fields) o

8XC251SA, SB, SP, SQ USER’S MANUALA-130Binary Mode Source ModeBytes: 21States (2 bytes): 11 10States (4 bytes): 16 15Hex Code in: Binary Mode = [A5][E

A-131INSTRUCTION SET REFERENCEXCH A,@RiBinary Mode Source ModeBytes: 12States: 45Hex Code in: Binary Mode = [Encoding]Source Mode = [A5][Encoding]Oper

8XC251SA, SB, SP, SQ USER’S MANUALA-132Binary Mode Source ModeBytes: 12States: 45Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operatio

A-133INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: XRL (dir8) ← (dir8) ∀ (A) XRL dir8,#dataBina

8XC251SA, SB, SP, SQ USER’S MANUALA-134XRL A,@RiBinary Mode Source ModeBytes: 12States: 23Hex Code in: Binary Mode = [Encoding]Source Mode = [A5][Enco

A-135INSTRUCTION SET REFERENCEOperation: XRL (WRds) ← (WRjd) ∀ (WRjs) XRL Rm,#dataBinary Mode Source ModeBytes: 43States: 32Hex Code in: Binary Mode =

8XC251SA, SB, SP, SQ USER’S MANUALA-136Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: XRL (WRj) ← (WRj) ∀ (dir8)XRL Rm,di

A-137INSTRUCTION SET REFERENCEXRL Rm,@DrkBinary Mode Source ModeBytes: 43States: 43[Encoding]Hex Code In: Binary Mode = [A5][Encoding]Source Mode = [E

2-7ARCHITECTURAL OVERVIEW2.2.3 Interrupt HandlerThe interrupt handler can receive interrupt requests from eleven sources: seven maskable sourcesand th

BSignal Descriptions

B-1APPENDIX BSIGNAL DESCRIPTIONSThis appendix provides reference information for the external signals of the 8XC251Sx. pin as-signments are shown in F

8XC251SA, SB, SP, SQ USER’S MANUALB-2Table B-1. PLCC/DIP Pin Assignments Listed by Functional CategoryAddress & Data Input/OutputName PLCC DIP Na

B-3SIGNAL DESCRIPTIONS Figure B-2. 8XC251SA, SB, SP, SQ 40-pin PDIP and Ceramic DIP Packages Table B-2. Signal Descriptions Signal NameType D

8XC251SA, SB, SP, SQ USER’S MANUALB-4CEX2:0CEX3CEX4I/O Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture

B-5SIGNAL DESCRIPTIONSRST I Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running resets the

8XC251SA, SB, SP, SQ USER’S MANUALB-6VSS2GND Secondary Ground 2. This ground is provided to reduce ground bounce and improve power supply bypassing. C

B-7SIGNAL DESCRIPTIONS Table B-3. Memory Signal Selections (RD1:0) RD1:0P1.7/CEX/A17/WCLKP3.7/RD#/A16/ PSEN# WR# Features0 0 A17 A16 Asserted f

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including in-fringement of any pate

8XC251SA, SB, SP, SQ USER’S MANUAL2-8The watchdog timer is a circuit that automatically resets the 8XC251Sx in the event of a hardwareor software upse

CRegisters

C-1APPENDIX CREGISTERSThis appendix is a reference source of information for the 8XC251Sx special function registers(SFRs) and the register file. The

8XC251SA, SB, SP, SQ USER’S MANUALC-2Table C-1. 8XC251SA, SB, SP, SQ SFR Map0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/FF8CH 00000000CCAP0HxxxxxxxxCCAP1HxxxxxxxxC

C-3REGISTERSTable C-2. Core SFRsMnemonic Name AddressACC†Accumulator S:E0HB†B Register S:F0HPSW Program Status Word S:D0HPSW1 Program Status Word 1 S

8XC251SA, SB, SP, SQ USER’S MANUALC-4Table C-4. Serial I/O SFRsMnemonic Name AddressSCON Serial Control S:98HSBUF Serial Data Buffer S:99HSADEN Slav

C-5REGISTERS Table C-6. Programmable Counter Array (PCA) SFRsMnemonic Name AddressCCON PCA Timer/Counter Control S:D8HCMOD PCA Timer/Counter Mod

8XC251SA, SB, SP, SQ USER’S MANUALC-6 Table C-7. Register File Mnemonic AddressR0 – R7 Four banks of 8 registers. Select bank 0-3 with bits RS1:0

C-7REGISTERS ACCAddress: E0HReset State: 0000 0000BAccumulator. ACC provides SFR access to the accumulator, which resides in the register fil

3Address Spaces

8XC251SA, SB, SP, SQ USER’S MANUALC-8 CCAPxH, CCAPxL (x = 0–4)Address: CCAP0H,L S:FAH, S:EAHCCAP1H,L S:FBH, S:EBHCCAP2H,L S:FCH, S:ECHCCAP3H,L

C-9REGISTERS CCAPMx (x = 0–4)Address: CCAPM0 S:DAHCCAPM1 S:DBHCCAPM2 S:DCHCCAPM3 S:DDHCCAPM4 S:DEHReset State: X000 0000BPCA Compare/Capture Modu

8XC251SA, SB, SP, SQ USER’S MANUALC-10 CCONAddress: S:D8HReset State: 00X0 0000BPCA Timer/Counter Control Register. Contains the run control

C-11REGISTERSCMODAddress: S:D9HReset State: 00XX X000BPCA Timer/Counter Mode Register. Contains bits for selecting the PCA timer/counter input, disabl

8XC251SA, SB, SP, SQ USER’S MANUALC-12 DPHAddress: S:83HReset State: 0000 0000BData Pointer High. DPH provides SFR access to register file locat

C-13REGISTERS DPXLAddress: S:84HReset State: 0000 0001BData Pointer Extended Low. DPXL provides SFR access to register file location 57 (also name

8XC251SA, SB, SP, SQ USER’S MANUALC-14 IE0Address: S:A8HReset State: 0000 0000BInterrupt Enable Register 0. IE0 contains two types of interrupt ena

C-15REGISTERS IPH0Address: S:B7HReset State: X000 0000BInterrupt Priority High Control Register 0. IPH0, together with IPL0, assigns each interrup

8XC251SA, SB, SP, SQ USER’S MANUALC-16 IPL0Address: S:B8HReset State: X000 0000BInterrupt Priority Low Control Register 0. IPL0, together with IPH

C-17REGISTERS P0Address: S:80HReset State: 1111 1111BPort 0. P0 is the SFR that contains data to be driven out from the port 0 pins. Read-modify-wr

8XC251SA, SB, SP, SQ USER’S MANUALC-18P2Address: S:A0HReset State: 1111 1111BPort 2. P2 is the SFR that contains data to be driven out from the port 2

C-19REGISTERSPCONAddress: S:87HReset State: 00XX 0000BPower Control Register. Contains the power off flag (POF) and bits for enabling the idle and pow

8XC251SA, SB, SP, SQ USER’S MANUALC-20 .PSWAddress: S:D0HReset State: 0000 0000BProgram Status Word. PSW contains bits that reflect the results of ope

C-21REGISTERS PSW1Address: S:D1HReset State: 0000 0000BProgram Status Word 1. PSW1 contains bits that reflect the results of operations and bi

8XC251SA, SB, SP, SQ USER’S MANUALC-22 SADDRAddress: S:A9HReset State: 0000 0000BSlave Individual Address Register. SADDR contains the device’s i

C-23REGISTERS SADENAddress: S:B9HReset State: 0000 0000BMask Byte Register. This register masks bits in the SADDR register to form the device’s

8XC251SA, SB, SP, SQ USER’S MANUALC-24SCONAddress: 98HReset State: 0000 0000BSerial Port Control Register. SCON contains serial I/O control and status

C-25REGISTERSSCONAddress: 98HReset State: 0000 0000BSerial Port Control Register. SCON contains serial I/O control and status bits, including the mode

8XC251SA, SB, SP, SQ USER’S MANUALC-26SPHAddress: S:BEHReset State: 0000 0000BStack Pointer High. SPH provides SFR access to location 62 in the regist

C-27REGISTERS T2CONAddress: S:C8HReset State: 0000 0000BTimer 2 Control Register. Contains the receive clock, transmit clock, and capture/reload

3-1CHAPTER 3ADDRESS SPACESMCS® 251 microcontrollers have three address spaces: a memory space, a special function reg-ister (SFR) space, and a registe

8XC251SA, SB, SP, SQ USER’S MANUALC-28 T2MODAddress: S:C9HReset State: XXXX XX00BTimer 2 Mode Control Register. Contains the timer 2 down count e

C-29REGISTERS TCONAddress: S:88HReset State: 0000 0000BTimer/Counter Control Register. Contains the overflow and external interrupt flags and the

8XC251SA, SB, SP, SQ USER’S MANUALC-30TMODAddress: S:89HReset State: 0000 0000BTimer/Counter Mode Control Register. Contains mode select, run control

C-31REGISTERS TH0, TL0Address: TH0 S:8CHTL0 S:8AHReset State: 0000 0000BTH0, TL0 Timer Registers. These registers operate in cascade to for

8XC251SA, SB, SP, SQ USER’S MANUALC-32 TH2, TL2Address: TH2 S:CDHTL2 S:CCHReset State: 0000 0000BTH2, TL2 Timer Registers. These registers ope

C-33REGISTERS WDTRSTAddress: S:A6HReset State: XXXX XXXXBWatchdog Timer Reset Register. Writing the two-byte sequence 1EH-E1H to the WDTRST regist

Glossary

Glossary-1GLOSSARYThis glossary defines acronyms, abbreviations, and terms that have special meaning in this man-ual. (Chapter 1, “Guide to this Manua

8XC251SA, SB, SP, SQ USER’S MANUAL3-2It is convenient to view the unsegmented, 16-Mbyte memory space as consisting of 256 64-Kbyteregions, numbered 00

8XC251SA, SB, SP, SQ USER’S MANUALGlossary-2big endien form Memory storage format in which the most significantbyte (MSB) of the word or double word i

Glossary-3GLOSSARYdeassert The term deassert refers to the act of making a signalinactive (disabled). The polarity (high/low) is definedby the signal

8XC251SA, SB, SP, SQ USER’S MANUALGlossary-4interrupt handler The module responsible for handling interrupts thatare to be serviced by user-written in

Glossary-5GLOSSARYnonpage mode Conventional method for accessing external memorywhere code fetches require a two-state bus cycle. Seealso page mode.np

8XC251SA, SB, SP, SQ USER’S MANUALGlossary-6set The term set refers to the value of a bit or the act ofgiving it a value. If a bit is set, its value i

Glossary-7GLOSSARYword A 16-bit unit of data. In memory, a word comprisestwo contiguous bytes.wraparound The result of interpreting an address whosehe

Index

Index-1#0data16, A-3#1data16, A-3#datadefinition, A-3#data16, A-3#short, A-38XC251SA, SB, SP, SQ, 1-1block diagram, 2-2on-chip peripherals, 2-

3-3ADDRESS SPACESThe register file (registers R0–R7) comprises four switchable register banks, each having eightregisters. The 32 bytes required for t

8XC251SA, SB, SP, SQ USER’S MANUALIndex-2CJNE instruction, A-25Clock, 2-6external, 11-4, 11-5external source, 11-3idle and powerdown modes, 12-5i

INDEXIndex-3ECI, 7-1EJMP instruction, 5-15, A-24EMAP# bit, 3-9, 4-16Encryption, 14-2Encryption arraykey bytes, 14-8programming, 14-1, 14-8setup

8XC251SA, SB, SP, SQ USER’S MANUALIndex-4detection, 6-3edge-triggered, 6-4enable/disable, 6-5exiting idle mode, 12-5exiting powerdown mode, 12-6e

INDEXIndex-5NN flag, 5-9, 5-19Noise reduction, 11-2, 11-3, 11-5Nonpage modebus cycles, See External bus cycles, Nonpage modebus structure, 13-1conf

8XC251SA, SB, SP, SQ USER’S MANUALIndex-6Phone numbers, customer support, 1-7Pin conditions, 12-3Pinsunused inputs, 11-2Pipeline, 2-5POP instructi

INDEXIndex-7RETI instruction, 6-1, 6-14, 6-15, A-24Return instructions, 5-15RL instruction, A-17RLC instruction, A-17ROM (on-chip), 14-1verifying

8XC251SA, SB, SP, SQ USER’S MANUALIndex-8T2, 7-1, 8-3T2CON, 3-17, 3-19, 8-1, 8-2, 8-10, 8-17, 10-13, C-2, C-4, C-27baud rate generator, 10-12T2EX,

INDEXIndex-9SFR (WDTRST), 3-19, C-4WCLK (Wait Clock) Output, 13-2WCON, 3-17, 13-11, C-2, C-3, C-32WDTRST, 3-17, 3-19, 8-2, 8-16, C-2, C-4, C-33Wor

8XC251SA, SB, SP, SQ USER’S MANUAL3-4Figure 3-3. Address Space Mappings MCS® 51 Architecture to MCS® 251 ArchitectureTable 3-1. Address Mappings Mem

3-5ADDRESS SPACESThe 64-Kbyte external data memory for MCS 51 microcontrollers is mapped into the memoryregion specified by bits 16–23 of the data poi

8XC251SA, SB, SP, SQ USER’S MANUAL3-6 Figure 3-4. 8XC251SA, SB, SP, SQ Address Space A4385-0101:FFFFHFE:FFFFHFF:FFFFH01:0000HFE:0000HFF:0000HMemo

3-7ADDRESS SPACES Figure 3-5. Hardware Implementation of the 8XC251SA, SB, SP, SQ Address SpaceA4382-0201:FFFFHFE:FFFFHFF:FFF7H01:0000HFE:0000HFF:

iiiCONTENTSCHAPTER 1GUIDE TO THIS MANUAL1.1 MANUAL CONTENTS ...

8XC251SA, SB, SP, SQ USER’S MANUAL3-8Locations FF:FFF8H–FF:FFFFH are reserved for the configuration array (see Chapter 4, “DeviceConfiguration”). The

3-9ADDRESS SPACESNOTEIf your program executes exclusively from on-chip ROM/OTPROM/EPROM (not from external memory), beware of executing code from the

8XC251SA, SB, SP, SQ USER’S MANUAL3-103.2.3 External MemoryRegions 01:, FE:, and portions of regions 00: and FF: of the memory space are implemented a

3-11ADDRESS SPACES Figure 3-6. The Register File A4099-01DR4DR0DR12DR81514131211109823222120191817163130292827262524Locations 32-55 are Reserved

8XC251SA, SB, SP, SQ USER’S MANUAL3-12Register file locations 0–7 actually consist of four switchable banks of eight registers each, as il-lustrated i

3-13ADDRESS SPACES3.3.1 Byte, Word, and Dword RegistersDepending on its location in the register file, a register is addressable as a byte, a word, an

8XC251SA, SB, SP, SQ USER’S MANUAL3-14Instructions in the MCS 51 architecture use the accumulator as the primary register for datamoves and calculatio

3-15ADDRESS SPACES3.3.2.2 Extended Data Pointer, DPXDword register DR56 is the extended data pointer, DPX (Figure 3-8). The lower three bytes ofDPX (D

8XC251SA, SB, SP, SQ USER’S MANUAL3-163.4 SPECIAL FUNCTION REGISTERS (SFRS)The special function registers (SFRs) reside in their associated on-chip pe

3-17ADDRESS SPACESTable 3-5. 8XC251SA, SB, SP, SQ SFR Map and Reset Values0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/FF8CH 00000000CCAP0HxxxxxxxxCCAP1HxxxxxxxxCCA

8XC251SA, SB, SP, SQ USER’S MANUALiv3.3.2.3 Extended Stack Pointer, SPX ...3

8XC251SA, SB, SP, SQ USER’S MANUAL3-18The following tables list the mnemonics, names, and addresses of the SFRs:Table 3-6 — Core SFRsTable 3-7 — I/O P

3-19ADDRESS SPACESTable 3-8. Serial I/O SFRsMnemonic Name AddressSCON Serial Control S:98HSBUF Serial Data Buffer S:99HSADEN Slave Address Mask S:B9

8XC251SA, SB, SP, SQ USER’S MANUAL3-20CL PCA Timer/Counter Low Byte S:E9HCH PCA Timer/Counter High Byte S:F9HCCAP0L PCA Compare/Capture Module 0 Lo

4DeviceConfiguration

4-1CHAPTER 4DEVICE CONFIGURATIONThe 8XC251Sx provides user design flexibility by configuring certain operating features at de-vice reset. These featur

8XC251SA, SB, SP, SQ USER’S MANUAL4-2For ROM/OTPROM/EPROM devices, user configuration bytes UCONFIG0 and UCONFIG1can be programmed at the factory or o

4-3DEVICE CONFIGURATION Figure 4-2. Configuration Array (External) A4236-011FF9H1FF8H8 Kbytes3FF9H3FF8H16 Kbytes7FF9H7FF8H32 KbytesFFF9HFFF8H64 Kby

8XC251SA, SB, SP, SQ USER’S MANUAL4-4 4.3 THE CONFIGURATION BITSThis section provides a brief description of the configuration bits contained in

4-5DEVICE CONFIGURATION4.4 CONFIGURATION BYTE LOCATION SELECTOR (UCON)The Configuration Byte Location Selector (UCON) applies only to OTPROM and EPROM

CONTENTSv5.4 BIT INSTRUCTIONS ... 5-115.4.1 Bit Addres

8XC251SA, SB, SP, SQ USER’S MANUAL4-6 Figure 4-3. Configuration Byte UCONFIG0UCONFIG0(1), (3)Address:FF:FFF8H (2)7 0UCON WSA1# WSA0# XALE# RD1 RD

4-7DEVICE CONFIGURATION Figure 4-4. Configuration Byte UCONFIG1UCONFIG1 (1), (3)Address:FF:FFF9H (2)7 0— — — INTR WSB WSB1# WSB0# EMAP#Bit Number

8XC251SA, SB, SP, SQ USER’S MANUAL4-8 4.5 CONFIGURING THE EXTERNAL MEMORY INTERFACEThis section describes the configuration options that affect th

4-9DEVICE CONFIGURATION4.5.2 Configuration Bits RD1:0The RD1:0 configuration bits (UCONFIG0.3:2) determine the number of external address signalsand t

8XC251SA, SB, SP, SQ USER’S MANUAL4-10This selection provides a 128-Kbyte external address space. The advantage of this selection, incomparison with t

4-11DEVICE CONFIGURATION Figure 4-6. Internal/External Address Mapping (RD1:0 = 10 and 11) FF:01:PSEN#RD#, WR#A4217-02FF:FE:01:00:RD1:0 = 1016 ex

8XC251SA, SB, SP, SQ USER’S MANUAL4-124.5.2.3 RD1:0 = 10 (16 External Address Bits) For RD1:0 = 10, the 16 external address bits (A15:0 on ports P0 an

4-13DEVICE CONFIGURATION4.5.3.3 Configuration Bit XALE#Clearing XALE# (UCONFIG0.4) extends the time ALE is asserted from TOSC to 3TOSC. This ac-commod

8XC251SA, SB, SP, SQ USER’S MANUAL4-14Figure 4-7 shows the opcode map for binary mode. Area I (columns 1 through 5 in Table A-6 onpage A-4) and area I

4-15DEVICE CONFIGURATIONFigure 4-7. Binary Mode Opcode Map Figure 4-8. Source Mode Opcode Map A4131-01I II0H 5H FH6H0HFHMCS® 51ArchitectureMCS 51A

8XC251SA, SB, SP, SQ USER’S MANUALvi8.2 TIMER/COUNTER OPERATION... 8-1

8XC251SA, SB, SP, SQ USER’S MANUAL4-164.7 MAPPING ON-CHIP CODE MEMORY TO DATA MEMORY (EMAP#)For devices with 16 Kbytes of on-chip code memory (87C251S

5Programming

5-1CHAPTER 5PROGRAMMINGThe instruction set for the MCS® 251 architecture is a superset of the instruction set for theMCS®51 architecture. This chapter

8XC251SA, SB, SP, SQ USER’S MANUAL5-25.2.1 Data TypesTable 5-1 lists the data types that are addressed by the instruction set. Words or dwords (double

5-3PROGRAMMING Figure 5-1. Word and Double-word Storage in Big Endien FormInstructions in the MCS 51 architecture use 80H–FFH as addresses for bot

8XC251SA, SB, SP, SQ USER’S MANUAL5-45.2.4 Addressing ModesThe MCS 251 architecture supports the following addressing modes:• register addressing: The

5-5PROGRAMMING5.3.1.1 Register AddressingBoth architectures address registers directly.• MCS 251 architecture. In the register addressing mode, the op

8XC251SA, SB, SP, SQ USER’S MANUAL5-65.3.1.4 IndirectIn arithmetic and logical instructions that use indirect addressing, the source operand is always

5-7PROGRAMMING Table 5-4. Addressing Modes for Data Instructions in the MCS® 251 ArchitectureMode Address Range of OperandAssembly Language Notat

CONTENTSvii10.2 MODES OF OPERATION... 10-410.2.1 Synchronous

8XC251SA, SB, SP, SQ USER’S MANUAL5-85.3.1.5 Displacement Several move instructions use displacement addressing to move bytes or words from a source t

5-9PROGRAMMINGThe MCS 251 architecture provides the MUL (multiply) and DIV (divide) instructions for un-signed 8-bit and 16-bit data (Table A-22 on pa

8XC251SA, SB, SP, SQ USER’S MANUAL5-105.3.4 Data Transfer InstructionsData transfer instructions copy data from one register or memory location to ano

5-11PROGRAMMING5.4 BIT INSTRUCTIONSA bit instruction addresses a specific bit in a memory location or SFR. There are four categoriesof bit instruction

8XC251SA, SB, SP, SQ USER’S MANUAL5-12Table 5-7 lists the addressing modes for bit instructions and Table A-26 on page A-23 summarizesthe bit instruct

5-13PROGRAMMING5.5.1 Addressing Modes for Control InstructionsTable 5-8 lists the addressing modes for the control instructions.• Relative addressing:

8XC251SA, SB, SP, SQ USER’S MANUAL5-145.5.2 Conditional JumpsThe MCS 251 architecture supports bit-conditional jumps, compare-conditional jumps, andju

5-15PROGRAMMING5.5.3 Unconditional JumpsThere are five unconditional jumps. NOP and SJMP jump to addresses relative to the programcounter. AJMP, LJMP,

8XC251SA, SB, SP, SQ USER’S MANUAL5-16RETI (Return from Interrupt) provides a return from an interrupt service routine. The operationof RETI depends o

5-17PROGRAMMINGTable 5-10. The Effects of Instructions on the PSW and PSW1 FlagsInstruction Type InstructionFlags Affected (1), (5)CY OV AC (2) N ZAr