Intel GD82559ER User Manual

GD82559ER Fast Ethernet** PCI ControllerNetworking SiliconDatasheetProduct Features Optimum Integration for Lowest Cost Solution—Integrated IEEE 802.

GD82559ER — Networking Silicon4 Datasheetoperate independently. Control is switched between the two units according to the microcode instruction flow.

Datasheet5Networking Silicon — GD82559ER2.3 10/100 Mbps Serial CSMA/CD Unit OverviewThe CSMA/CD unit of the 82559ER allows it to be connected to eithe

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Datasheet7Networking Silicon —GD82559ER3. Signal Descriptions3.1 Signal Type Definitions3.2 PCI Bus Interface Signals3.2.1 Address and Data SignalsTyp

GD82559ER — Networking Silicon8Datasheet3.2.2 Interface Control SignalsSymbol Type Name and FunctionFRAME# S/T/SCycle Frame. The cycle frame signal is

Datasheet9Networking Silicon —GD82559ER3.2.3 System and Power Management Signals3.3 Local Memory Interface SignalsSymbol Type Name and FunctionCLK INC

GD82559ER — Networking Silicon10Datasheet3.4 Testability Port SignalsFLA[13]/EEDIOUTFlash Address[13]/EEPROM Data Input. During Flash accesses, this m

Datasheet11Networking Silicon —GD82559ER3.5 PHY SignalsNOTE:619 Ω and 549 Ω for the RBIAS100 and RBIAS10, respectively, are only a recommended values

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Datasheet 13Networking Silicon — GD82559ER4. GD82559ER Media Access Control Functional Description4.1 82559ER InitializationThe 82559ER has four sourc

GD82559ER - Networking SiliconiiDatasheetInformation in this document is provided in connection with Intel products. No license, express or implied, b

GD82559ER — Networking Silicon14 Datasheet4.2 PCI Interface4.2.1 82559ER Bus OperationsAfter configuration, the 82559ER is ready for normal operation.

Datasheet 15Networking Silicon — GD82559ERThe figures below show CSR zero wait-state I/O read and write cycles. In the case of accessing the Control/S

GD82559ER — Networking Silicon16 Datasheetcontrols the TRDY# signal and asserts it from the data access. The 82559ER allows the CPU to issue only one

Datasheet 17Networking Silicon — GD82559ERWrite Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable li

GD82559ER — Networking Silicon18 DatasheetNote:The 82559ER is considered the target in the above diagram; thus, TRDY# is not asserted.4.2.1.1.4 Error

Datasheet 19Networking Silicon — GD82559ER8 depict memory read and write burst cycles. For bus master cycles, the 82559ER is the initiator and the hos

GD82559ER — Networking Silicon20 DatasheetByte Count value indicates the maximum number of transmit DMA PCI cycles that will be completed after an 825

Datasheet 21Networking Silicon — GD82559ER1. Minimum transfer of one cache line2. Active byte enable bits (or BE#[3:0] are all low) during MWI access3

GD82559ER — Networking Silicon22 Datasheet•This feature is not recommended for use in non-cache line oriented systems since it may cause shorter burst

Datasheet 23Networking Silicon — GD82559ER4.2.4 Power StatesThe 82559ER’s power management register implements all four power states as defined in the

DatasheetiiiNetworking Silicon — GD82559ERContents1. INTRODUCTION...

GD82559ER — Networking Silicon24 Datasheet4.2.4.4 D3 Power StateIn the D3 power state, the 82559ER has the same capabilities and consumes the same amo

Datasheet 25Networking Silicon — GD82559ER.4.2.4.6 Auxiliary Power SignalThe 82559ER senses whether it is connected to the PCI power supply or to an a

GD82559ER — Networking Silicon26 DatasheetIn a LAN on Motherboard solution, the PCI power good signal is supplied by the system. In network adapter im

Datasheet 27Networking Silicon — GD82559ER•ISOLATE# trailing edgeThe internal initialization signal resets the PCI Configuration Space, MAC configurat

GD82559ER — Networking Silicon28 Datasheet4.2.5.2 Link Status Change EventThe 82559ER link status indication circuit is capable of issuing a PME on a

Datasheet 29Networking Silicon — GD82559ERAll accesses, either read or write, are preceded by a command instruction to the device. The address field i

GD82559ER — Networking Silicon30 DatasheetNote that word 0Ah contains several configuration bits. Bits from word 0Ah, FBh through FEh, and certain bit

Datasheet 31Networking Silicon — GD82559ER4.5.1 Full DuplexWhen operating in full duplex mode the 82559ER can transmit and receive frames simultaneous

GD82559ER — Networking Silicon32 Datasheet4.6 Media Independent Interface (MII) Management InterfaceThe MII management interface allows the CPU to con

Datasheet33Networking Silicon — GD82559ER5. GD82559ER Test Port Functionality5.1 Introduction The 82559ER’s NAND-Tree Test Access Port (TAP) is the ac

GD82559ER — Networking Siliconiv Datasheet6.1.2 100BASE-TX Transmit Blocks ...37

GD82559ER — Networking Silicon34Datasheet5.5 TriStateThis command set all 82559ER Input and Output pins into a TRI-state (HIGH-Z) mode, all internal p

Datasheet35Networking Silicon — GD82559ER19 STOP# FLD220 GNT# FLD321 PERR# FLD422 PAR FLD523 AD16 FLD624 C/BE1# FLD725 AD15 FLA026 AD14 FLA127 AD13 FL

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Datasheet 37Networking Silicon — GD82559ER6. GD82559ER Physical Layer Functional Description6.1 100BASE-TX PHY Unit6.1.1 100BASE-TX Transmit Clock Gen

GD82559ER — Networking Silicon38 Datasheet6.1.2.2 100BASE-TX Scrambler and MLT-3 EncoderData is scrambled in 100BASE-TX to reduce electromagnetic emi

Datasheet 39Networking Silicon — GD82559ER6.1.2.3 100BASE-TX Transmit FramingThe PHY unit does not differentiate between the fields of the MAC frame c

GD82559ER — Networking Silicon40 Datasheet6.1.3 100BASE-TX Receive BlocksThe receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the

Datasheet 41Networking Silicon — GD82559ER6.1.4 100BASE-TX Collision Detection100BASE-TX collisions in half duplex mode only are detected similarly to

GD82559ER — Networking Silicon42 Datasheet6.2.2 10BASE-T Transmit Blocks6.2.2.1 10BASE-T Manchester EncoderAfter the 2.5 MHz clocked data is serializ

Datasheet 43Networking Silicon — GD82559ERAll other activity is determined to be either data, link test pulses, Auto-Negotiation fast link pulses, or

DatasheetvNetworking Silicon — GD82559ER8.1.10 Flow Control Register...

GD82559ER — Networking Silicon44 Datasheet6.3.1 DescriptionAuto-Negotiation selects the fastest operating mode (in other words, the highest common de

Datasheet 45Networking Silicon — GD82559ERwill perform Auto-Negotiation or Parallel Detection with no data packets being transmitted. Connection is th

GD82559ER — Networking Silicon46 DatasheetFigure 16. Two and Three LED Schematic DiagramLILEDACTLEDVCCSpeedLEDLILEDACTLEDSpeedLED82559ER

Datasheet47Networking Silicon — GD82559ER7. PCI Configuration RegistersThe 82559ER acts as both a master and a slave on the PCI bus. As a master, the

GD82559ER — Networking Silicon48Datasheet7.1.2 PCI Command RegisterThe 82559ER Command register at word address 04h in the PCI configuration space pro

Datasheet49Networking Silicon — GD82559ER7.1.3 PCI Status RegisterThe 82559ER Status register is used to record status information for PCI bus related

GD82559ER — Networking Silicon50Datasheet7.1.4 PCI Revision ID RegisterThe Revision ID is an 8-bit read only register with a default value of 08h for

Datasheet51Networking Silicon — GD82559ERNote:Bit 3 is set to 1b only if the value 00001000b (8H) is written to this register, and bit 4 is set to 1b

GD82559ER — Networking Silicon52DatasheetNote:Bit 0 in all base registers is read only and used to determine whether the register maps into memory or

Datasheet53Networking Silicon — GD82559ER7.1.10 PCI Subsystem Vendor ID and Subsystem ID RegistersThe Subsystem Vendor ID field identifies the vendor

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GD82559ER — Networking Silicon54Datasheet7.1.13 Interrupt Pin RegisterThe Interrupt Pin register is read only and defines which of the four PCI interr

Datasheet55Networking Silicon — GD82559ER7.1.19 Power Management Control/Status Register (PMCSR)The Power Management Control/Status is a word register

GD82559ER — Networking Silicon56Datasheet7.1.20 Data RegisterThe data register is an 8-bit read only register that provides a mechanism for the 82559E

Datasheet57Networking Silicon — GD82559ER8. Control/Status Registers8.1 LAN (Ethernet) Control/Status RegistersThe 82559ER’s Control/Status Register (

GD82559ER — Networking Silicon58DatasheetMDI Control Register: The MDI Control register allows the CPU to read and write information from the PHY unit

Datasheet59Networking Silicon — GD82559ER8.1.2 System Control Block Command WordCommands for the 82559ER’s Command and Receive units are placed in thi

GD82559ER — Networking Silicon60Datasheet8.1.8 Receive Direct Memory Access Byte CountThe Receive DMA Byte Count register keeps track of how many byte

Datasheet61Networking Silicon — GD82559ERNote:The PMDR is initialized at ALTRST# reset only.8.1.12 General Control RegisterThe General Control registe

GD82559ER — Networking Silicon62Datasheet8.2 Statistical CountersThe 82559ER provides information for network management statistics by providing on-ch

Datasheet63Networking Silicon — GD82559ERThe Statistical Counters are initially set to zero by the 82559ER after reset. They cannot be preset to anyth

Datasheet1Networking Silicon — GD82559ER1. Introduction1.1 GD82559ER OverviewThe 82559ER is part of Intel's second generation family of fully int

GD82559ER — Networking Silicon64Datasheet

Datasheet65Networking Silicon — GD82559ER9. PHY Unit RegistersThe 82559ER provides status and accepts management information via the Management Data I

GD82559ER — Networking Silicon66 Datasheet9.1.2 Register 1: Status Register Bit Definitions 9 Restart Auto-NegotiationThis bit restarts the Auto-Negot

Datasheet67Networking Silicon — GD82559ER9.1.3 Register 2: PHY Identifier Register Bit Definitions 9.1.4 Register 3: PHY Identifier Register Bit Defin

GD82559ER — Networking Silicon68 Datasheet9.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions 9.2 MDI Registers 8 - 15Registers eigh

Datasheet69Networking Silicon — GD82559ER9.3.2 Register 17: PHY Unit Special Control Bit Definitions 8 Polarity This bit indicates 10BASE-T polarity.1

GD82559ER — Networking Silicon70 Datasheet9.3.3 Register 18: PHY Address Register9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Defin

Datasheet71Networking Silicon — GD82559ER9.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions 9.3.9 Register 24:

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Datasheet73Networking Silicon — GD82559ER10. Electrical and Timing Specifications10.1 Absolute Maximum RatingsMaximum ratings are listed below:Case Te

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GD82559ER — Networking Silicon74 DatasheetNOTES:1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input b

Datasheet75Networking Silicon — GD82559ERNOTES: Current is measured on all VCC pins (VCC = 3.3 V).1. Transmitter peak current is attained by dividing

GD82559ER — Networking Silicon76 Datasheet10.3 AC SpecificationsNOTES:1. Switching Current High specifications are not relevant to PME#, SERR#, or INT

Datasheet77Networking Silicon — GD82559ER10.4 Timing Specifications10.4.1 Clocks Specifications10.4.1.1 PCI Clock SpecificationsThe 82559ER uses the P

GD82559ER — Networking Silicon78 Datasheet10.4.2 Timing Parameters10.4.2.1 Measurement and Test ConditionsFigure 27, Figure 28, and Table 24 define th

Datasheet79Networking Silicon — GD82559ERNOTE:Input test is done with 0.1VCC overdrive. Vmax specifies the maximum peak-to-peak waveform allowed for t

GD82559ER — Networking Silicon80 DatasheetNOTES:1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150

Datasheet81Networking Silicon — GD82559ER10.4.2.4 EEPROM Interface TimingsThe 82559ER is designed to support a standard 64x16, or 256x16 serial EEPROM

GD82559ER — Networking Silicon82 Datasheet10.4.2.5 PHY Timings Figure 30. EEPROM TimingsEECSFLA15EESKFLA13EEDIT51 T52T54T53Table 28. 10BASE-T NLP Timi

Datasheet83Networking Silicon — GD82559ERFigure 32. Auto-Negotiation FLP TimingsFast Link PulseT60T58T59Clock PulseData PulseClock PulseFLP BurstsT62T

Datasheet3Networking Silicon — GD82559ER2. GD82559ER Architectural OverviewFigure 1 is a high level block diagram of the 82559ER. It is divided into f

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Datasheet85Networking Silicon — GD82559ER12. Package and Pinout Information12.1 Package InformationThe GD82559ER is a 196-pin Ball Grid Array (BGA) pa

GD82559ER — Networking Silicon86 Datasheet12.2 Pinout Information12.2.1 GD82559ER Pin Assignments Table 15. GD82559ER Pin AssignmentsPin Name Pin Name

Datasheet87Networking Silicon — GD82559ERH1 STOP# H2 INTA# H3 DEVSEL#H4 NC H5 VCC H6 VCCH7 VCC H8 VCC H9 VSSH10 VSS H11 VSS H12 FLD6H13 FLD5 H14 FLD4J

GD82559ER — Networking Silicon88 Datasheet12.2.2 GD82559ER Ball Grid Array Diagram Figure 25. GD82559ER Ball Grid Array DiagramNCFLA9VCCPLX2FLA13/EEDI